公开(公告)号：US20240256332A1

公开(公告)日：2024-08-01

申请号：US18160523

申请日：2023-01-27

Applicant: Arm Limited

Inventor： Elliot Maurice Simon Rosemarine

IPC: G06F9/48

CPC classification number: G06F9/4881

Abstract: Briefly, example methods, apparatuses, and/or articles of manufacture are disclosed that may facilitate and/or support scheduling tasks for one or more hardware components of a computing device.

公开(公告)号：US20240256281A1

公开(公告)日：2024-08-01

申请号：US18101726

申请日：2023-01-26

Applicant: Arm Limited

Inventor： Quentin Éric NOUVEL ,  Luca NASSI ,  Adrien PESLE

IPC: G06F9/38

CPC classification number: G06F9/384

Abstract: A data processing apparatus comprises: execution circuitry to execute instructions in order to perform data processing operations specified by those instructions; a plurality of registers to store data values for access by the execution circuitry when performing the data processing operations, each register having an associated physical register identifier; register rename circuitry to select physical register identifiers to associate with architectural register identifiers specified by the instructions; and rename storage having a plurality of entries, each entry being associated with one of the architectural register identifiers and used by the register rename circuitry to indicate a physical register identifier selected for association with that one of the architectural register identifiers; the register rename circuitry comprising an execute unit, and being responsive to detection of an early execute condition for a given instruction, the early execute condition requiring at least detection that each source value required to execute the given instruction is available to the register rename circuitry without accessing the plurality of registers, to cause the execute unit to perform the data processing operation specified by the given instruction in order to generate a result value, and to cause the generated result value to be stored in an entry of the rename storage associated with a destination architectural register identifier specified by the given instruction.

公开(公告)号：US20240248764A1

公开(公告)日：2024-07-25

申请号：US18316602

申请日：2023-05-12

Applicant: Arm Limited

Inventor： Rune HOLM ,  Jens OLSON ,  Elliot Maurice Simon ROSEMARINE ,  Jared SMOLENS

IPC: G06F9/50

CPC classification number: G06F9/5038 ,  G06F9/505 ,  G06F2209/5021

Abstract: A memory unit configured for handling task data, the task data describing a task to be executed as a directed acyclic graph of operations, wherein each operation maps to a corresponding execution unit, and wherein each connection between operations in the acyclic graph maps to a corresponding storage element of the execution unit. The task data defines an operation space representing the dimensions of a multi-dimensional arrangement of the connected operations to be executed represented by the data blocks; the memory unit configured to receive a sequence of processing requests comprising the one or more data blocks with each data block assigned a priority value and comprising a block command. The memory unit is configured to arbitrate between the data blocks based upon the priority value and block command to prioritize the sequence of processing requests and wherein the processing requests include writing data to, or reading data from storage.

公开(公告)号：US12047083B2

公开(公告)日：2024-07-23

申请号：US17519490

申请日：2021-11-04

Applicant: Arm Limited

Inventor： El Mehdi Boujamaa ,  Benoit Labbe ,  David Michael Bull

IPC: H03L7/091 ,  G06F1/08 ,  G06F1/12 ,  H03L7/081

CPC classification number: H03L7/091 ,  G06F1/08 ,  G06F1/12 ,  H03L7/0814

Abstract: In one particular implementation, a circuit includes: a flip flop; and an AND gate, where the circuit is configured to generate edge-triggered set and reset input signals. In another implementation, a method includes: providing, by a digital locked loop (DLL), a plurality of phase outputs; determining, by respective logic circuits, respective pulses to be selected for an output clock corresponding to each of the plurality phase outputs; shifting respective selection windows of the pulses such that each of the selection windows fully overlap the corresponding respective determined pulses; and selecting the pulses.

公开(公告)号：US12045618B2

公开(公告)日：2024-07-23

申请号：US17209515

申请日：2021-03-23

Applicant: Arm Limited

Inventor： Natalya Bondarenko ,  Stefano Ghiggini ,  Geoffray Matthieu Lacourba ,  Cédric Denis Robert Airaud

IPC: G06F9/38 ,  G06N20/00

CPC classification number: G06F9/3802 ,  G06F9/383 ,  G06N20/00

Abstract: The invention provides a data processing apparatus and a data processing method for generating prefetches of data for use during execution of instructions by processing circuitry. The prefetches that are generated are based on a nested prefetch pattern. The nested prefetch pattern comprises a first pattern and a second pattern. The first pattern is defined by a first address offset between sequentially accessed addresses and a first observed number of the sequentially accessed addresses separated by the first address offset. The second pattern is defined by a second address offset between sequential iterations of the first pattern and a second observed number of the sequential iterations of the first pattern separated by the second address offset.

公开(公告)号：US20240242314A1

公开(公告)日：2024-07-18

申请号：US18622311

申请日：2024-03-29

Applicant: Arm Limited

Inventor： Liam James O'Neil ,  Joshua James Sowerby ,  Matthew James Wash ,  Samuel James Edward Martin

IPC: G06T5/70 ,  G06N3/08

CPC classification number: G06T5/70 ,  G06N3/08 ,  G06T2207/20081 ,  G06T2207/20084

Abstract: Example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, techniques to select between and/or among multiple available alternative approaches to perform a temporal anti-aliasing operation in processing an image.

公开(公告)号：US20240241755A1

公开(公告)日：2024-07-18

申请号：US18098334

申请日：2023-01-18

Applicant: Arm Limited

Inventor： Richard Andrew PATERSON ,  Jonathan BAKER

IPC: G06F9/50 ,  G06F9/46 ,  G06F9/54

CPC classification number: G06F9/5033 ,  G06F9/466 ,  G06F9/544

Abstract: An apparatus and method for controlling access to a shared resource accessible to a plurality of initiator components is provided. The apparatus has shared resource management circuitry to select, from amongst the plurality of initiator components, a currently granted initiator component that is currently allowed to access the shared resource, and to identify the currently granted initiator component within a storage structure. Gating circuitry is located in a communication path between the given initiator component and the shared resource which, on receipt of a given transaction initiated by a given initiator component, determines with reference to the storage structure whether the given initiator component is the currently granted initiator component. The gating circuitry is arranged, when the currently granted initiator component is the given initiator component, to allow onward propagation of the given transaction to the shared resource, and is arranged, when the currently granted initiator component is other than the given initiator component, to block onward propagation of the given transaction to the shared resource and to trigger a recovery action to seek to facilitate future handling of the given transaction.

公开(公告)号：US12038846B2

公开(公告)日：2024-07-16

申请号：US17593319

申请日：2020-01-03

Applicant: Arm Limited

Inventor： Andreas Lars Sandberg ,  Stephan Diestelhorst

IPC: G06F12/1009 ,  G06F12/0817

CPC classification number: G06F12/1009 ,  G06F12/0817

Abstract: A page table structure for address translation may include a relative type of page table entry, for which an address pointer to a next-level page table entry or a translated address may be specified using a relative offset value indicating an offset of the address pointer relative to a reference-point base address.

公开(公告)号：US20240233814A9

公开(公告)日：2024-07-11

申请号：US17971226

申请日：2022-10-21

Applicant: Arm Limited

Inventor： Vianney Antoine Choserot ,  Andy Wangkun Chen ,  Yew Keong Chong ,  Sriram Thyagarajan

IPC: G11C11/412 ,  G11C11/418 ,  G11C11/419

CPC classification number: G11C11/412 ,  G11C11/418 ,  G11C11/419

Abstract: Various implementations described herein are related to a device having a storage node with a bitcell. The device may have a first stage that performs a first write based on an internal bitline signal, a first write wordline signal and a second write wordline signal. The first stage outputs the internal bitline signal. The device may have a second stage that receives the internal bitline signal and performs a second write of the internal bitline signal to the bitcell. The device may have a third stage with write wordline ports and write bitline ports. The third stage provides the internal bitline signal based on a selected write wordline signal from a write wordline port of the write wordline ports and based on a selected bitline signal based on a write bitline port of the write bitline ports.

公开(公告)号：US20240220269A1

公开(公告)日：2024-07-04

申请号：US18261966

申请日：2022-01-19

Applicant: Arm Limited

Inventor： Mbou Eyole ,  Giacomo Gabrielli ,  Balaji Venu

IPC: G06F9/38

CPC classification number: G06F9/3853

Abstract: Circuitry comprises processing circuitry configured to execute program instructions in dependence upon respective trigger conditions matching a current trigger state and to set a next trigger state in response to program instruction execution; the processing circuitry comprising: instruction storage configured to selectively provide a group of two or more program instructions for execution in parallel; and trigger circuitry responsive to the generation of a trigger state by execution of program instructions and to a trigger condition associated with a given group of program instructions, to control the instruction storage to provide program instructions of the given group of program instructions for execution.