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81.发明申请公开(公告)号：US20100270607A1
公开(公告)日：2010-10-28
申请号：US12831323
申请日：2010-07-07
IPC分类号： H01L29/788
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： It is made possible to provide a memory device that can be made very small in size and have a high capacity while being able to effectively suppress short-channel effects. A nonvolatile semiconductor memory device includes: a first insulating film formed on a semiconductor substrate; a semiconductor layer formed above the semiconductor substrate so that the first insulating film is interposed between the semiconductor layer and the semiconductor substrate; a NAND cell having a plurality of memory cell transistors connected in series, each of the memory cell transistors having a gate insulating film formed on the semiconductor layer, a floating gate formed on the gate insulating film, a second insulating film formed on the floating gate, and a control gate formed on the second insulating film; a source region having an impurity diffusion layer formed in one side of the NAND cell; and a drain region having a metal electrode formed in the other side of the NAND cell.
摘要翻译： 可以提供一种可以制造尺寸非常小并且具有高容量的存储器件，同时能够有效地抑制短沟道效应。 非易失性半导体存储器件包括：形成在半导体衬底上的第一绝缘膜; 半导体层，其形成在所述半导体衬底上方，使得所述第一绝缘膜插入在所述半导体层和所述半导体衬底之间; 具有串联连接的多个存储单元晶体管的NAND单元，每个存储单元晶体管具有形成在所述半导体层上的栅极绝缘膜，形成在所述栅极绝缘膜上的浮置栅极，形成在所述浮动栅极上的第二绝缘膜 以及形成在所述第二绝缘膜上的控制栅极; 源区，其具有形成在NAND单元的一侧的杂质扩散层; 以及在NAND单元的另一侧形成有金属电极的漏极区域。
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82.发明授权公开(公告)号：US07777270B2
公开(公告)日：2010-08-17
申请号：US11835694
申请日：2007-08-08
IPC分类号： H01L29/788
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： It is made possible to provide a memory device that can be made very small in size and have a high capacity while being able to effectively suppress short-channel effects. A nonvolatile semiconductor memory device includes: a first insulating film formed on a semiconductor substrate; a semiconductor layer formed above the semiconductor substrate so that the first insulating film is interposed between the semiconductor layer and the semiconductor substrate; a NAND cell having a plurality of memory cell transistors connected in series, each of the memory cell transistors having a gate insulating film formed on the semiconductor layer, a floating gate formed on the gate insulating film, a second insulating film formed on the floating gate, and a control gate formed on the second insulating film; a source region having an impurity diffusion layer formed in one side of the NAND cell; and a drain region having a metal electrode formed in the other side of the NAND cell.
摘要翻译： 可以提供一种可以制造尺寸非常小并且具有高容量的存储器件，同时能够有效地抑制短沟道效应。 非易失性半导体存储器件包括：形成在半导体衬底上的第一绝缘膜; 半导体层，其形成在所述半导体衬底上方，使得所述第一绝缘膜插入在所述半导体层和所述半导体衬底之间; 具有串联连接的多个存储单元晶体管的NAND单元，每个存储单元晶体管具有形成在所述半导体层上的栅极绝缘膜，形成在所述栅极绝缘膜上的浮置栅极，形成在所述浮动栅极上的第二绝缘膜 以及形成在所述第二绝缘膜上的控制栅极; 源区，其具有形成在NAND单元的一侧的杂质扩散层; 以及在NAND单元的另一侧形成有金属电极的漏极区域。
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公开(公告)号：US07774162B2
公开(公告)日：2010-08-10
申请号：US12015147
申请日：2008-01-16
CPC分类号： G04F10/10
摘要： A system LSI including a semiconductor chip which receives power from a power supply, and an electronic timer which measures a time from an interruption of power supplying to the semiconductor chip to a resumption of power supplying to the semiconductor chip.
摘要翻译： 包括从电源接收电力的半导体芯片的系统LSI和测量从半导体芯片的供电中断恢复向半导体芯片供电的时间的电子计时器。
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公开(公告)号：US20090325357A1
公开(公告)日：2009-12-31
申请号：US12585034
申请日：2009-09-01
申请人： Atsuhiro Kinoshita , Junji Koga
发明人： Atsuhiro Kinoshita , Junji Koga
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L29/1045 , H01L29/1083 , H01L29/665 , H01L29/6653
摘要： A semiconductor device which can effectively suppress a short channel effect and junction leakage is provided. A semiconductor device includes a field effect transistor. The field effect transistor includes a first semiconductor region of a first conductivity type, a gate electrode formed on a gate insulating film, and source and drain electrodes. The field effect transistor also includes second semiconductor regions of a second conductivity type. The field effect transistor further includes third semiconductor regions of the second conductivity type having an impurity concentration higher than that of the second semiconductor region and formed between the source electrode and the first and second semiconductor regions and between the drain electrode and the first and second semiconductor regions, and side wall insulating films formed on both the side surfaces of the gate electrode. The source electrode and the drain electrode are separated from the side wall insulating films.
摘要翻译： 提供了可以有效地抑制短通道效应和结漏电的半导体器件。 半导体器件包括场效应晶体管。 场效应晶体管包括第一导电类型的第一半导体区域，形成在栅极绝缘膜上的栅极电极以及源极和漏极电极。 场效应晶体管还包括第二导电类型的第二半导体区域。 场效应晶体管还包括具有比第二半导体区域的杂质浓度高的第二导电类型的第三半导体区域，并且形成在源电极和第一和第二半导体区域之间以及在漏电极和第一和第二半导体之间 区域和形成在栅电极的两个侧表面上的侧壁绝缘膜。 源电极和漏电极与侧壁绝缘膜分离。
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85.发明申请SEMICONDUCTOR DEVICE WITH CARBON NANOTUBE CHANNEL AND MANUFACTURING METHOD THEREOF 审中-公开具有碳纳米管通道的半导体器件及其制造方法公开(公告)号：US20080315183A1
公开(公告)日：2008-12-25
申请号：US12052229
申请日：2008-03-20
申请人： Atsuhiro KINOSHITA , Yoshifumi Nishi , Ken Uchida , Junji Koga
发明人： Atsuhiro KINOSHITA , Yoshifumi Nishi , Ken Uchida , Junji Koga
IPC分类号： H01L29/12 , H01L21/336
CPC分类号： H01L51/105 , B82Y10/00 , H01L51/0048 , H01L51/0512 , H01L51/0541 , H01L51/0545
摘要： A high-performance semiconductor device having a channel region structured from a carbon nanotube (CNT) for reducing or minimizing a drain leakage current is provided. This semiconductor device includes, in addition to the CNT-formed channel region, a gate electrode formed to overlie the channel region with a gate insulation film sandwiched therebetween, and a pair of source and drain regions interposing the channel region therebetween. The source and drain regions have portions in contact with the channel region, which portions are made of a specific semiconductor material that is wider in energy band gap than the channel region.
摘要翻译： 提供了一种具有由碳纳米管（CNT）构成的沟道区，用于降低或最小化漏极漏电流的高性能半导体器件。 除了CNT形成的沟道区域之外，该半导体器件还包括形成为覆盖沟道区域的栅电极，其间夹有栅极绝缘膜，并且在其间插入沟道区域的一对源极和漏极区域。 源极区和漏极区具有与沟道区接触的部分，这些部分由能量带隙比通道区宽的特定半导体材料制成。
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公开(公告)号：US07456096B2
公开(公告)日：2008-11-25
申请号：US11530724
申请日：2006-09-11
申请人： Takashi Yamauchi , Atsuhiro Kinoshita , Yoshinori Tsuchiya , Junji Koga , Koichi Kato , Nobutoshi Aoki , Kazuya Ohuchi
发明人： Takashi Yamauchi , Atsuhiro Kinoshita , Yoshinori Tsuchiya , Junji Koga , Koichi Kato , Nobutoshi Aoki , Kazuya Ohuchi
IPC分类号： H01L29/45
CPC分类号： H01L21/28537 , H01L21/265 , H01L21/28052 , H01L21/28518 , H01L29/41791 , H01L29/66143 , H01L29/66643 , H01L29/66795 , H01L29/7833 , H01L29/7839 , H01L29/785 , H01L29/872 , H01L2029/7858
摘要： It is made possible to reduce the interface resistance at the interface between the nickel silicide film and the silicon. A semiconductor manufacturing method includes: forming an impurity region on a silicon substrate, with impurities being introduced into the impurity region; depositing a Ni layer so as to cover the impurity region; changing the surface of the impurity region into a NiSi2 layer through annealing; forming a Ni layer on the NiSi2 layer; and silicidating the NiSi2 layer through annealing.
摘要翻译： 可以降低硅化镍膜与硅之间界面处的界面电阻。 半导体制造方法包括：在硅衬底上形成杂质区域，杂质被引入杂质区域; 沉积Ni层以覆盖杂质区域; 通过退火将杂质区的表面改变成NiSi 2层; 在NiSi 2层上形成Ni层; 并通过退火对NiSi 2层进行硅化。
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公开(公告)号：US20080150040A1
公开(公告)日：2008-06-26
申请号：US12034822
申请日：2008-02-21
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L29/66643 , H01L29/66795 , H01L29/7839 , H01L29/78621
摘要： An field effect transistor includes a first semiconductor region, a gate electrode insulatively disposed over the first semiconductor region, source and drain electrodes between which the first semiconductor region is sandwiched, and second semiconductor regions each formed between the first semiconductor region and one of the source and drain electrodes, and having impurity concentration higher than that of the first semiconductor region, the source electrode being offset to the gate electrode in a direction in which the source electrode and the drain electrode are separated from each other with respect to a channel direction, and one of the second semiconductor regions having a thickness not more than a thickness with which the one of second semiconductor regions is completely depleted in the channel direction being in thermal equilibrium with the source electrode therewith.
摘要翻译： 场效应晶体管包括第一半导体区域，绝缘地设置在第一半导体区域上的栅极电极，夹在第一半导体区域之间的源极和漏极电极以及形成在第一半导体区域和源极之一之间的第二半导体区域 和漏电极，其杂质浓度高于第一半导体区域，源电极在源电极和漏电极相对于沟道方向彼此分离的方向上偏移到栅电极， 并且所述第二半导体区域中的一个具有不大于所述第二半导体区域中的所述第二半导体区域在所述沟道方向上完全耗尽的厚度的厚度与所述源极电极处于热平衡。
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公开(公告)号：US07358550B2
公开(公告)日：2008-04-15
申请号：US11081348
申请日：2005-03-16
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L29/66643 , H01L29/66795 , H01L29/7839 , H01L29/78621
摘要： An field effect transistor includes a first semiconductor region, a gate electrode insulatively disposed over the first semiconductor region, source and drain electrodes between which the first semiconductor region is sandwiched, and second semiconductor regions each formed between the first semiconductor region and one of the source and drain electrodes, and having impurity concentration higher than that of the first semiconductor region, the source electrode being offset to the gate electrode in a direction in which the source electrode and the drain electrode are separated from each other with respect to a channel direction, and one of the second semiconductor regions having a thickness not more than a thickness with which the one of second semiconductor regions is completely depleted in the channel direction being in thermal equilibrium with the source electrode therewith.
摘要翻译： 场效应晶体管包括第一半导体区域，绝缘地设置在第一半导体区域上的栅极电极，夹在第一半导体区域之间的源极和漏极电极以及形成在第一半导体区域和源极之一之间的第二半导体区域 和漏电极，其杂质浓度高于第一半导体区域，源电极在源电极和漏电极相对于沟道方向彼此分离的方向上偏移到栅电极， 并且所述第二半导体区域中的一个具有不大于所述第二半导体区域中的所述第二半导体区域在所述沟道方向上完全耗尽的厚度的厚度与所述源极电极处于热平衡。
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公开(公告)号：US20070298558A1
公开(公告)日：2007-12-27
申请号：US11738687
申请日：2007-04-23
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L21/26513 , H01L21/28097 , H01L21/823814 , H01L21/823835 , H01L29/665 , H01L29/6659 , H01L29/66628 , H01L29/66636
摘要： A semiconductor device includes a first semiconductor region of first type conductivity with a channel region being formed therein, a gate electrode insulatively formed above the channel region, a layer of SixGe1-x (0
摘要翻译： 一种半导体器件包括：第一类型导电性的第一半导体区域，其中形成沟道区;绝缘地形成在沟道区上方的栅电极，一层Si x 1-x < / SUB>（0
层以具有范围为10 21至10 22原子/ cm 3的受控杂质浓度，以及上述含镍硅化物层 第二个半导体区域。 还公开了半导体器件的制造方法。 -
90.发明申请公开(公告)号：US20070291539A1
公开(公告)日：2007-12-20
申请号：US11699334
申请日：2007-01-30
IPC分类号： G11C11/34 , H01L21/822
CPC分类号： H01L27/115 , H01L27/11556 , H01L27/11568
摘要： A nonvolatile semiconductor memory device includes a semiconductor substrate, plural semiconductor columns arranged in a matrix form on the substrate, plural first conductive areas zonally formed in a column direction on the substrate between the semiconductor columns and functioning as word lines, plural second conductive areas formed at tops of the semiconductor columns, respectively, plural bit lines connecting the second conductive areas in a row direction, plural channel areas respectively formed in the semiconductor columns between the first and second conductive areas and contacting the first and second conductive areas, plural third conductive areas continuously formed via first insulating films above the substrate and opposite to the channel areas in the column direction between the semiconductor columns and functioning as control gates, and plural charge accumulation areas respectively formed via second insulating films at upper portions of the channel areas at a position higher than the third conductive areas.
摘要翻译： 非易失性半导体存储器件包括：半导体衬底，以矩阵形式布置在衬底上的多个半导体柱，在半导体柱之间的衬底上的列方向上分区形成的多个第一导电区域，并且用作字线，形成多个第二导电区域 在半导体柱的顶部分别分别连接在行方向上的第二导电区域的多个位线，分别形成在第一和第二导电区域之间的半导体柱中并与第一和第二导电区域接触的多个沟道区域，多个第三导电 通过基板上方的第一绝缘膜连续形成的区域，并且与半导体柱之间的列方向上的沟道区域相对，并且用作控制栅极，以及分别在沟道区域的上部经由第二绝缘膜形成的多个电荷累积区域 位置高 她比第三个导电区域。
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