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公开(公告)号：US20080150040A1
公开(公告)日：2008-06-26
申请号：US12034822
申请日：2008-02-21
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L29/66643 , H01L29/66795 , H01L29/7839 , H01L29/78621
摘要： An field effect transistor includes a first semiconductor region, a gate electrode insulatively disposed over the first semiconductor region, source and drain electrodes between which the first semiconductor region is sandwiched, and second semiconductor regions each formed between the first semiconductor region and one of the source and drain electrodes, and having impurity concentration higher than that of the first semiconductor region, the source electrode being offset to the gate electrode in a direction in which the source electrode and the drain electrode are separated from each other with respect to a channel direction, and one of the second semiconductor regions having a thickness not more than a thickness with which the one of second semiconductor regions is completely depleted in the channel direction being in thermal equilibrium with the source electrode therewith.
摘要翻译： 场效应晶体管包括第一半导体区域，绝缘地设置在第一半导体区域上的栅极电极，夹在第一半导体区域之间的源极和漏极电极以及形成在第一半导体区域和源极之一之间的第二半导体区域 和漏电极，其杂质浓度高于第一半导体区域，源电极在源电极和漏电极相对于沟道方向彼此分离的方向上偏移到栅电极， 并且所述第二半导体区域中的一个具有不大于所述第二半导体区域中的所述第二半导体区域在所述沟道方向上完全耗尽的厚度的厚度与所述源极电极处于热平衡。
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公开(公告)号：US07358550B2
公开(公告)日：2008-04-15
申请号：US11081348
申请日：2005-03-16
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L29/66643 , H01L29/66795 , H01L29/7839 , H01L29/78621
摘要： An field effect transistor includes a first semiconductor region, a gate electrode insulatively disposed over the first semiconductor region, source and drain electrodes between which the first semiconductor region is sandwiched, and second semiconductor regions each formed between the first semiconductor region and one of the source and drain electrodes, and having impurity concentration higher than that of the first semiconductor region, the source electrode being offset to the gate electrode in a direction in which the source electrode and the drain electrode are separated from each other with respect to a channel direction, and one of the second semiconductor regions having a thickness not more than a thickness with which the one of second semiconductor regions is completely depleted in the channel direction being in thermal equilibrium with the source electrode therewith.
摘要翻译： 场效应晶体管包括第一半导体区域，绝缘地设置在第一半导体区域上的栅极电极，夹在第一半导体区域之间的源极和漏极电极以及形成在第一半导体区域和源极之一之间的第二半导体区域 和漏电极，其杂质浓度高于第一半导体区域，源电极在源电极和漏电极相对于沟道方向彼此分离的方向上偏移到栅电极， 并且所述第二半导体区域中的一个具有不大于所述第二半导体区域中的所述第二半导体区域在所述沟道方向上完全耗尽的厚度的厚度与所述源极电极处于热平衡。
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公开(公告)号：US07479674B2
公开(公告)日：2009-01-20
申请号：US12034822
申请日：2008-02-21
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L29/66643 , H01L29/66795 , H01L29/7839 , H01L29/78621
摘要： An field effect transistor includes a first semiconductor region, a gate electrode insulatively disposed over the first semiconductor region, source and drain electrodes between which the first semiconductor region is sandwiched, and second semiconductor regions each formed between the first semiconductor region and one of the source and drain electrodes, and having impurity concentration higher than that of the first semiconductor region, the source electrode being offset to the gate electrode in a direction in which the source electrode and the drain electrode are separated from each other with respect to a channel direction, and one of the second semiconductor regions having a thickness not more than a thickness with which the one of second semiconductor regions is completely depleted in the channel direction being in thermal equilibrium with the source electrode therewith.
摘要翻译： 场效应晶体管包括第一半导体区域，绝缘地设置在第一半导体区域上的栅极电极，夹在第一半导体区域之间的源极和漏极电极以及形成在第一半导体区域和源极之一之间的第二半导体区域 和漏电极，其杂质浓度高于第一半导体区域，源电极在源电极和漏电极相对于沟道方向彼此分离的方向上偏移到栅电极， 并且所述第二半导体区域中的一个具有不大于所述第二半导体区域中的所述第二半导体区域在所述沟道方向上完全耗尽的厚度的厚度与所述源极电极处于热平衡。
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公开(公告)号：US20050212055A1
公开(公告)日：2005-09-29
申请号：US11081348
申请日：2005-03-16
IPC分类号： H01L29/417 , H01L21/00 , H01L21/336 , H01L29/76 , H01L29/772 , H01L29/78 , H01L29/786
CPC分类号： H01L29/785 , H01L29/66643 , H01L29/66795 , H01L29/7839 , H01L29/78621
摘要： An field effect transistor includes a first semiconductor region, a gate electrode insulatively disposed over the first semiconductor region, source and drain electrodes between which the first semiconductor region is sandwiched, and second semiconductor regions each formed between the first semiconductor region and one of the source and drain electrodes, and having impurity concentration higher than that of the first semiconductor region, the source electrode being offset to the gate electrode in a direction in which the source electrode and the drain electrode are separated from each other with respect to a channel direction, and one of the second semiconductor regions having a thickness not more than a thickness with which the one of second semiconductor regions is completely depleted in the channel direction being in thermal equilibrium with the source electrode therewith.
摘要翻译： 场效应晶体管包括第一半导体区域，绝缘地设置在第一半导体区域上的栅极电极，夹在第一半导体区域之间的源极和漏极电极以及形成在第一半导体区域和源极之一之间的第二半导体区域 和漏电极，其杂质浓度高于第一半导体区域，源电极在源电极和漏电极相对于沟道方向彼此分离的方向上偏移到栅电极， 并且所述第二半导体区域中的一个具有不大于所述第二半导体区域中的所述第二半导体区域在所述沟道方向上完全耗尽的厚度的厚度与所述源极电极处于热平衡。
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5.发明申请公开(公告)号：US20060091433A1
公开(公告)日：2006-05-04
申请号：US11260252
申请日：2005-10-28
申请人： Kazumi Nishinohara
发明人： Kazumi Nishinohara
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7856
摘要： A semiconductor integrated circuit device includes a projected semiconductor layer formed at a part of the upper surface of a semiconductor substrate; a gate insulation film formed on a first side surface of the semiconductor layer; a gate electrode formed on the gate insulation film; a first insulation film formed on a second side surface of the semiconductor layer; and a source region and a drain region formed within the semiconductor layer to sandwich the gate electrode, wherein the first insulation film has a larger thickness than that of the gate insulation film.
摘要翻译： 半导体集成电路器件包括形成在半导体衬底的上表面的一部分处的投影半导体层; 形成在所述半导体层的第一侧表面上的栅极绝缘膜; 形成在栅极绝缘膜上的栅电极; 形成在所述半导体层的第二侧表面上的第一绝缘膜; 以及形成在所述半导体层内以夹持所述栅电极的源区和漏区，其中所述第一绝缘膜的厚度大于所述栅极绝缘膜的厚度。
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公开(公告)号：US06541829B2
公开(公告)日：2003-04-01
申请号：US09726486
申请日：2000-12-01
IPC分类号： H01L2976
CPC分类号： H01L29/66583 , H01L21/823807 , H01L27/092 , H01L29/105 , H01L29/66537 , H01L29/66545 , H01L29/66628
摘要： A semiconductor device has a first semiconductor region formed in a semiconductor substrate and having a first conductivity type due to first-conductivity-type active impurities contained in the first semiconductor region, and a second semiconductor region formed between the first semiconductor region and the surface of the semiconductor substrate and having a second conductivity type due to second-conductivity-type active impurities contained in the second semiconductor region. The second semiconductor region contains first-conductivity-type active impurities whose concentration is zero or smaller than a quarter of a concentration of the second-conductivity-type active impurities contained in the second semiconductor region. An insulating film and a conductor are formed on the second semiconductor region. Third and fourth semiconductor regions of the second conductivity type are formed at the semiconductor surface in contact with the side faces of the second semiconductor region. This semiconductor device is capable of suppressing net impurity concentration variations as well as threshold voltage variations to be caused by a short channel effect or manufacturing variations.
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7.发明授权公开(公告)号：US07584011B2
公开(公告)日：2009-09-01
申请号：US12007723
申请日：2008-01-15
IPC分类号： G06F19/00
CPC分类号： G05B19/41885 , G05B2219/45031 , Y02P90/20 , Y02P90/26
摘要： A method for optimizing a structure of an industrial product includes selecting control factors from among manufacturing parameters affecting a target characteristic, which is scheduled to be manufactured by a sequence of manufacturing processes; setting levels to the respective control factors; selecting a reference characteristic having a trade-off relation with the target characteristic from among characteristics of the structure; setting a reference value to the reference characteristic; selecting a prior adjustment factor affecting the reference characteristic; creating conditions for experiments assigning combinations of the levels to the respective control factors; determining an adjustment value of the prior adjustment factor so that each of characteristic values of the reference characteristic obtained by the experiments conforms substantially to the reference value; and determining experimental characteristic values of the target characteristic using the adjustment value.
摘要翻译： 一种用于优化工业产品结构的方法包括从影响目标特性的制造参数中选择控制因子，该目标特性被安排由一系列制造过程制造; 设定各个控制因素的水平; 从结构的特征中选择具有与目标特性的权衡关系的参考特征; 将参考值设置为参考特性; 选择影响参考特征的先前调整因子; 创建将各级的组合分配给各个控制因素的实验条件; 确定现有调整因子的调整值，使得通过实验获得的参考特性的每个特征值基本上符合参考值; 以及使用所述调整值来确定所述目标特性的实验特性值。
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8.发明申请公开(公告)号：US20070067056A1
公开(公告)日：2007-03-22
申请号：US11480373
申请日：2006-07-05
IPC分类号： G06F19/00
CPC分类号： G05B19/41885 , G05B2219/45031 , Y02P90/20 , Y02P90/26
摘要： A method for optimizing a structure of an industrial product includes selecting control factors from among manufacturing parameters affecting a target characteristic, which is scheduled to be manufactured by a sequence of manufacturing processes; setting levels to the respective control factors; selecting a reference characteristic having a trade-off relation with the target characteristic from among characteristics of the structure; setting a reference value to the reference characteristic; selecting a prior adjustment factor affecting the reference characteristic; creating conditions for experiments assigning combinations of the levels to the respective control factors; determining an adjustment value of the prior adjustment factor so that each of characteristic values of the reference characteristic obtained by the experiments conforms substantially to the reference value; and determining experimental characteristic values of the target characteristic using the adjustment value.
摘要翻译： 一种用于优化工业产品结构的方法包括从影响目标特性的制造参数中选择控制因子，该目标特性被安排由一系列制造过程制造; 设定各个控制因素的水平; 从结构的特征中选择具有与目标特性的权衡关系的参考特征; 将参考值设置为参考特性; 选择影响参考特征的先前调整因子; 创建将各级的组合分配给各个控制因素的实验条件; 确定现有调整因子的调整值，使得通过实验获得的参考特性的每个特征值基本上符合参考值; 以及使用所述调整值来确定所述目标特性的实验特性值。
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公开(公告)号：US06812104B2
公开(公告)日：2004-11-02
申请号：US10236947
申请日：2002-09-09
申请人： Kazumi Nishinohara
发明人： Kazumi Nishinohara
IPC分类号： H01L21336
CPC分类号： H01L29/66621 , H01L29/66545 , H01L29/66628 , H01L29/7834
摘要： A MIS type semiconductor device comprises a semiconductor layer provided with a recess portion having a side wall with an obtuse angle at least at a portion of the recess portion, a gate electrode formed over a bottom surface of the recess portion, with a gate insulating film interposed, a source region and a drain region formed on sides of the gate electrode with an insulating film interposed, such that boundary planes between the source region and the drain region, on one hand, and the insulating film, on the other hand, are formed in the semiconductor layer at an angle to a surface of the semiconductor layer, and wiring portions for contact with the surface of the semiconductor layer. Wherein an edge of the gate electrode is located inside the recess portion provided in the semiconductor layer, and there is provided at least one of a mutually opposed portion between the gate electrode and the source region and a mutually opposed portion between the gate electrode and the drain region, whereby at least one of a portion of the source region and a portion of the drain region, which lie in the associated mutually opposed portions, functions as an accumulation layer.
摘要翻译： MIS型半导体器件包括半导体层，该半导体层设置有至少在凹部的一部分处具有钝角的侧壁的凹部，形成在凹部的底面的栅电极，栅极绝缘膜 插入有形成在栅电极的侧面上的源极区域和漏极区域，绝缘膜插入，另一方面，源极区域和漏极区域之间的边界面以及绝缘膜是 在半导体层中以与半导体层的表面成一定角度的方式形成，以及用于与半导体层的表面接触的布线部分。 其中栅电极的边缘位于设置在半导体层中的凹部内部，并且在栅电极和源极区之间设置相互相对的部分中的至少一个以及栅电极和栅电极之间的相互对置的部分 漏极区域，由此位于相关联的相对部分中的源极区域的一部分和漏极区域的一部分中的至少一个用作累积层。
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公开(公告)号：US07078776B2
公开(公告)日：2006-07-18
申请号：US10867797
申请日：2004-06-16
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66583 , H01L21/823807 , H01L27/092 , H01L29/105 , H01L29/66537 , H01L29/66545 , H01L29/66628
摘要： A semiconductor device has a first semiconductor region formed in a semiconductor substrate and having a first conductivity type due to first-conductivity-type active impurities contained in the first semiconductor region, and a second semiconductor region formed between the first semiconductor region and the surface of the semiconductor substrate and having a second conductivity type due to second-conductivity-type active impurities contained in the second semiconductor region. The second semiconductor region contains first-conductivity-type active impurities, whose concentration is zero or smaller than a quarter of a concentration of the second-conductivity-type active impurities contained in the second semiconductor region. An insulating film and a conductor are formed on the second semiconductor region. Third and fourth semiconductor regions of the second conductivity type are formed at the semiconductor surface in contact with the side faces of the second semiconductor region. This semiconductor device is capable of suppressing net impurity concentration variations as well as threshold voltage variations to be caused by a short channel effect or manufacturing variations.
摘要翻译： 半导体器件具有形成在半导体衬底中并且由于第一半导体区域中包含的第一导电型有源杂质而具有第一导电类型的第一半导体区域，以及形成在第一半导体区域和第一半导体区域之间的第二半导体区域 并且由于第二半导体区域中包含的第二导电型有源杂质而具有第二导电类型。 第二半导体区域包含第一导电型有源杂质，其浓度为零或小于第二半导体区域中所含的第二导电型有源杂质浓度的四分之一。 绝缘膜和导体形成在第二半导体区域上。 在与第二半导体区域的侧面接触的半导体表面处形成第二导电类型的第三和第四半导体区域。 该半导体器件能够抑制净杂质浓度变化以及由短沟道效应或制造变化引起的阈值电压变化。
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