公开(公告)号：US20080288900A1

公开(公告)日：2008-11-20

申请号：US11841079

申请日：2007-08-20

Applicant: Cheng-Ta Hsieh ,  Yifeng Wang ,  Yung-Te Lai ,  Chih-Chang Lin

Inventor： Cheng-Ta Hsieh ,  Yifeng Wang ,  Yung-Te Lai ,  Chih-Chang Lin

IPC: G06F17/50

CPC classification number: G06F17/505

Abstract: Some aspects provide determination of a function to rectify functional differences between netlist G1 and netlist G2 having inputs V. The determination may include determination of a signal s of netlist G1 that can be re-synthesized so as to correct the functional differences between netlist G1 and netlist G2, assignment of respective static values to a first plurality of inputs V, assignment of respective initial values to a second plurality of inputs V, determination of a first function based on the assigned static values, the assigned initial values, a first error function reflecting the difference between outputs of netlist G1 and netlist G2 for each vector of inputs V in a case that s equals 0, and a second error function reflecting the difference between the outputs of netlist G1 and netlist G2 for each vector of inputs V in a case that s equals 1. Also included may be determination of whether the first function rectifies the functional differences between netlist G1 and netlist G2, assignment, if it is determined that the first function does not rectify the functional differences, of respective next values to the second plurality of inputs, and determination of a second function based on the first function, the assigned static values, the assigned next values, the first error function, and the second error function.

Abstract translation: 一些方面提供了确定具有输入V的网表G 1＆lt; 1＆gt;和网表G 2 2之间的功能差异的功能。该确定可以包括网表G的信号s的确定， 可以重新合成以便校正网表G 1和网表G 2 2之间的功能差异的SUB> 1 ，将各个静态值分配给 第一多个输入V，将各个初始值分配给第二多个输入V，基于所分配的静态值确定第一功能，分配的初始值，反映网表G 和网表G 2 。还包括确定 如果确定第一功能不排除功能差异，则第一功能是否纠正网表G 1＆lt; 1＆lt; 1＆gt;和网表G 2 2之间的功能差异， 相应的第二多个输入的下一个值，以及基于第一功能确定第二功能，分配的静态值，分配的下一个值，第一误差函数和第二误差函数。

公开(公告)号：US20070294649A1

公开(公告)日：2007-12-20

申请号：US11847177

申请日：2007-08-29

Applicant: Manish Pandey ,  Yung-Te Lai ,  Bret Siarkowski ,  Kei-Yong Khoo ,  Chih-Chang Lin

Inventor： Manish Pandey ,  Yung-Te Lai ,  Bret Siarkowski ,  Kei-Yong Khoo ,  Chih-Chang Lin

IPC: G06F17/50

CPC classification number: G06F17/504

Abstract: Some embodiments relate to a method and apparatus for performing logic equivalence checking (EC) of circuits using adaptive learning based on a persistent cache containing information on sub-problems solved from previous equivalency checking runs. These sub-problems can include basic EC tasks such as logic cone comparison and/or state element mapping.

Abstract translation: 一些实施例涉及一种用于使用基于包含从先前等效检查运行解决的子问题的信息的持久高速缓存来执行使用自适应学习的电路的逻辑等价性检查（EC）的方法和装置。 这些子问题可以包括基本的EC任务，例如逻辑锥比较和/或状态元素映射。

公开(公告)号：US07067957B2

公开(公告)日：2006-06-27

申请号：US10745592

申请日：2003-12-29

Applicant: Chin-Wen Chou ,  Eddie Cheng ,  Kuang-Ming Wu ,  Chih-Chang Lin

Inventor： Chin-Wen Chou ,  Eddie Cheng ,  Kuang-Ming Wu ,  Chih-Chang Lin

IPC: H01L41/107

CPC classification number: H05B41/2828 ,  H01L41/044

Abstract: A ceramic transformer level driving circuit mainly aims to transform a low voltage signal to another low voltage signal through an amplified signal to drive a medium voltage system. It includes a control unit to generate a resonant frequency and output phase signal waveforms, a waveform transformation unit to provide phase signals and perform waveform phase transformation for the phase signal waveforms, and a medium voltage driving circuit which includes a floating level unit and a driving unit which receives a medium voltage electric input. The driving unit actuates opening and closing at different time to enable the floating level unit to output a voltage floating level thereby to drive a ceramic transformer to control the medium voltage system through a low voltage level.

Abstract translation: 陶瓷变压器电平驱动电路主要是通过放大信号将低电压信号转换为另一低电压信号，以驱动中压系统。 它包括产生谐振频率和输出相位信号波形的控制单元，提供相位信号并对相位信号波形执行波形相位变换的波形变换单元，以及包括浮置电平单元和驱动的中压驱动电路 接收中压电输入的单元。 驱动单元在不同时间启动打开和关闭，以使浮动水平单元能够输出电压浮动电平，从而驱动陶瓷变压器以通过低电压电平控制中压系统。

公开(公告)号：US20050155002A1

公开(公告)日：2005-07-14

申请号：US10995658

申请日：2004-11-22

Applicant: Yung-Te Lai ,  Chioumin Chang ,  Kung-Chien Chen ,  Chih-Chang Lin

Inventor： Yung-Te Lai ,  Chioumin Chang ,  Kung-Chien Chen ,  Chih-Chang Lin

IPC: G06F17/50

CPC classification number: G06F17/5022 ,  G06F17/504

Abstract: An equivalence checking method provides first and second logic functions. Don't care gates are inserted for don't care conditions in the first and second logic functions. The insertion of the don't care gates creates a first intermediate circuit and a second intermediate circuit. All 3DC gates of the first intermediate circuit are propagated and merged into a single 3DC gate when 3DC gates and SDC gates coexist in either of the first and second intermediate circuits. All 3DC gates of the second intermediate circuit are propagated and merged into a single 3DC gate when 3DC gates and SDC gates coexist in either of the first and second intermediate circuits. First and second circuit are produced in response to propagating and merging the 3DC gates. A combinational equivalence check is then performed of the first circuit to the second circuit under different equivalence relations.

Abstract translation: 等价检查方法提供第一和第二逻辑功能。 不要在第一和第二逻辑功能中插入无门的条件。 无关门的插入产生第一中间电路和第二中间电路。 当3DC门和SDC门共存在第一和第二中间电路中时，第一中间电路的所有3DC门被传播并合并成单个3DC门。 当3DC门和SDC门共存在第一和第二中间电路中时，第二中间电路的所有3DC门都被传播并合并成单个3DC门。 响应于3DC门的传播和合并而产生第一和第二电路。 然后在不同的等价关系下对第二电路执行第一电路的组合等价检查。

公开(公告)号：US06742174B1

公开(公告)日：2004-05-25

申请号：US10037844

申请日：2001-10-19

Applicant: Kuang-Chien Chen ,  Chih-Chang Lin ,  Cheng-Ta Hsieh ,  Yifeng Wang

Inventor： Kuang-Chien Chen ,  Chih-Chang Lin ,  Cheng-Ta Hsieh ,  Yifeng Wang

IPC: G06F1750

CPC classification number: G06F17/5022

Abstract: A method for modeling a circuit design includes synthesizing the circuit design to create a first gate-level representation of the circuit design. The method also includes analyzing a second gate-level representation of the circuit design to learn architecture information, and resynthesizing the first gate-level representation of the circuit design to incorporate the learned architecture information from the second gate-level representation of the circuit design. A computer-readable storage medium has stored thereon computer instructions that, when executed by a computer, cause the computer to synthesize a circuit design to create a first gate-level representation of the circuit design. The computer instructions also cause the computer to analyze a second gate-level representation of the circuit design to learn architecture information, and resynthesize the first gate-level representation of the circuit design to incorporate the learned architecture information from the second gate-level representation of the circuit design.

Abstract translation: 用于对电路设计进行建模的方法包括合成电路设计以创建电路设计的第一门级表示。 该方法还包括分析电路设计的第二门级表示以学习架构信息，以及重新合成电路设计的第一门级表示，以从电路设计的第二门级表示中并入所学习的体系结构信息。 计算机可读存储介质上存储有计算机指令，其在由计算机执行时使计算机合成电路设计以创建电路设计的第一门级表示。 计算机指令还使得计算机分析电路设计的第二门级表示以学习架构信息，并重新合成电路设计的第一门级表示，以将来自第二门级表示的学习架构信息 电路设计。

公开(公告)号：US09134360B2

公开(公告)日：2015-09-15

申请号：US13547101

申请日：2012-07-12

Applicant: Tao Wen Chung ,  Chan-Hong Chern ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Yuwen Swei

Inventor： Tao Wen Chung ,  Chan-Hong Chern ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Yuwen Swei

IPC: H03L5/00 ,  G01R31/26

CPC classification number: G01R31/2621

Abstract: A circuit has a first circuit module including a first resistor and first and second transistors coupled in parallel with the first resistor. The first resistor and the first and second transistors are coupled together at a first node. An equivalent resistance across the first circuit module increases as a voltage of the first node is increased from a first voltage to a second voltage, and the equivalent resistance across the first circuit module decreases as the voltage of the first node is increased from the second voltage to a third voltage.

Abstract translation: 电路具有包括第一电阻器和与第一电阻器并联耦合的第一和第二晶体管的第一电路模块。 第一电阻器和第一和第二晶体管在第一节点耦合在一起。 当第一节点的电压从第一电压增加到第二电压时，跨第一电路模块的等效电阻增加，并且第一电路模块上的等效电阻随着第一节点的电压从第二电压增加而减小 到第三电压。

公开(公告)号：US08896352B2

公开(公告)日：2014-11-25

申请号：US13278742

申请日：2011-10-21

Applicant: Ming-Chieh Huang ,  Tao Wen Chung ,  Chan-Hong Chern ,  Chih-Chang Lin ,  Yuwen Swei ,  Chiang Pu

Inventor： Ming-Chieh Huang ,  Tao Wen Chung ,  Chan-Hong Chern ,  Chih-Chang Lin ,  Yuwen Swei ,  Chiang Pu

IPC: H03K3/00

CPC classification number: H03H11/44 ,  H01S5/0427 ,  H04B10/504

Abstract: A driver includes a first driver stage having at least one input node and at least one first output node. The first driver stage includes a T-coil structure that is disposed adjacent to the at least one first output node. The T-coil structure includes a first set of inductors each being operable to provide a first inductance. A second set of inductors are electrically coupled with the first set of inductors in a parallel fashion. The second set of inductors each are operable to provide a second inductance. A second driver stage is electrically coupled with the first driver stage.

Abstract translation: 驱动器包括具有至少一个输入节点和至少一个第一输出节点的第一驱动器级。 第一驱动级包括邻近于至少一个第一输出节点设置的T型线圈结构。 T型线圈结构包括第一组电感器，每个电感器可操作以提供第一电感。 第二组电感器以并行方式与第一组电感器电耦合。 第二组电感器可操作以提供第二电感。 第二驱动级与第一驱动器级电耦合。

公开(公告)号：US08816732B2

公开(公告)日：2014-08-26

申请号：US13530136

申请日：2012-06-22

Applicant: Chan-Hong Chern ,  Tao Wen Chung ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Tsung-Ching Huang ,  Fu-Lung Hsueh

Inventor： Chan-Hong Chern ,  Tao Wen Chung ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Tsung-Ching Huang ,  Fu-Lung Hsueh

IPC: H03L7/06

CPC classification number: H03L7/103 ,  H03L7/097 ,  H03L7/0995 ,  H03L7/1072 ,  H03L7/18 ,  H03L2207/06

Abstract: A circuit includes a capacitive-load voltage controlled oscillator having an input configured to receive a first input signal and an output configured to output an oscillating output signal. A calibration circuit is coupled to the voltage controlled oscillator and is configured to output one or more control signals to the capacitive-load voltage controlled oscillator for adjusting a frequency of the oscillating output signal. The calibration circuit is configured to output the one or more control signals in response to a comparison of an input voltage to at least one reference voltage.

Abstract translation: 电路包括电容负载压控振荡器，其具有被配置为接收第一输入信号的输入和被配置为输出振荡输出信号的输出。 校准电路耦合到压控振荡器，并被配置为将一个或多个控制信号输出到电容负载压控振荡器，用于调整振荡输出信号的频率。 校准电路被配置为响应于输入电压与至少一个参考电压的比较而输出一个或多个控制信号。

公开(公告)号：US20140038085A1

公开(公告)日：2014-02-06

申请号：US13562436

申请日：2012-07-31

Applicant: Chan-Hong Chern ,  Tao Wen Chung ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Tsung-Ching (Jim) Huang ,  Fu-Lung Hsueh

Inventor： Chan-Hong Chern ,  Tao Wen Chung ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Tsung-Ching (Jim) Huang ,  Fu-Lung Hsueh

IPC: G06F17/50 ,  G03F1/68

CPC classification number: G03F7/70466 ,  G03F7/70433 ,  G06F17/5077

Abstract: Some aspects of the present disclosure provide for a method of automatically balancing mask misalignment for multiple patterning layers to minimize the consequences of mask misalignment. In some embodiments, the method defines a routing grid for one or more double patterning layers within an IC layout. The routing grid has a plurality of vertical grid lines extending along a first direction and a plurality of horizontal grid lines extending along a second, orthogonal direction. Alternating lines of the routing grid in a given direction (e.g., the horizontal and vertical direction) are assigned different colors. Shapes on the double patterning layers are then routed along the routing grid in a manner that alternates between different colored grid lines. By routing in such a manner, variations in capacitive coupling caused by mask misalignment are reduced.

Abstract translation: 本公开的一些方面提供了一种自动平衡多个图案化层的掩模未对准的方法，以最小化掩模未对准的后果。 在一些实施例中，该方法定义了IC布局内的一个或多个双图案化层的布线网格。 路由网格具有沿着第一方向延伸的多个垂直网格线和沿着第二正交方向延伸的多个水平网格线。 在给定方向（例如，水平和垂直方向）上布线网格的交替线被分配不同的颜色。 然后双重图案化层上的形状沿着布线网格以不同颜色的网格线之间交替的方式布线。 通过以这种方式进行布线，减少了由掩模未对准引起的电容耦合的变化。

公开(公告)号：US20140028407A1

公开(公告)日：2014-01-30

申请号：US13558670

申请日：2012-07-26

Applicant: Chan-Hong Chern ,  Tao Wen Chung ,  Chih-Chang Lin ,  Ming-Chieh Huang ,  Tsung-Ching Huang ,  Fu-Lung Hsueh

Inventor： Chan-Hong Chern ,  Tao Wen Chung ,  Chih-Chang Lin ,  Ming-Chieh Huang ,  Tsung-Ching Huang ,  Fu-Lung Hsueh

IPC: H03B5/12

CPC classification number: G06F1/10 ,  H03B5/12 ,  H03B5/32 ,  H03K5/15

Abstract: The present disclosure relates to a resonant clock system having a driver component, a clock load capacitor, and a reconfigurable inductor array. The driver component generates a driven input signal. The clock load capacitor is configured to receive the driven input signal. The inductor array is configured to have an effective inductance according to a selected frequency. The inductor array also generates a resonant signal at the selected frequency using the effective inductance.

Abstract translation: 本公开涉及具有驱动器部件，时钟负载电容器和可重构电感器阵列的谐振时钟系统。 驱动器组件产生驱动输入信号。 时钟负载电容器被配置为接收驱动输入信号。 电感器阵列被配置为具有根据选定频率的有效电感。 电感器阵列还使用有效电感在选定频率处产生谐振信号。