公开(公告)号：US6001687A

公开(公告)日：1999-12-14

申请号：US283849

申请日：1999-04-01

申请人： Wen-Ting Chu ,  Di-Son Kuo ,  Chrong-Jung Lin ,  Hung-Der Su ,  Jong Chen

发明人： Wen-Ting Chu ,  Di-Son Kuo ,  Chrong-Jung Lin ,  Hung-Der Su ,  Jong Chen

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L21/8239

CPC分类号： H01L27/11521

摘要： When FLASH cells are made in association with STI (as opposed to LOCOS) it is often the case that stringers of silicon nitride are left behind after the spacers have been formed. This problem has been eliminated by requiring that the oxide in the STI trenches remain in place at the time that the silicon nitride spacers are formed. After that, the oxide is removed in the usual manner, following which a SALICIDE process is used to form a self aligned source line. When this sequence is followed no stringers are left behind on the walls of the trench, guaranteeing the absence of any open circuits or high resistance regions in the source line.

摘要翻译： 当与STI（与LOCOS相反）制成FLASH单元时，通常在形成间隔物之后留下氮化硅桁条。 通过要求在形成氮化硅间隔物的时刻STI槽中的氧化物保持在适当位置，已经消除了这个问题。 之后，以通常的方式去除氧化物，随后使用SALICIDE工艺来形成自对准的源极线。 当遵循该顺序时，沟槽的壁上不留下桁条，保证在源极线中不存在任何开路或高电阻区域。

公开(公告)号：US5970371A

公开(公告)日：1999-10-19

申请号：US110418

申请日：1998-07-06

申请人： Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Yai-Fen Lin ,  Chuang-Ke Yeh ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Yai-Fen Lin ,  Chuang-Ke Yeh ,  Di-Son Kuo

IPC分类号： H01L21/336 ,  H01L29/423

CPC分类号： H01L29/66825 ,  H01L29/42324

摘要： A method is provided for forming a split-gate flash memory cell having a sharp beak of poly which substantially improves the programming erase speed of the cell. The sharp beak is formed through an extra and judicious wet etch of the polyoxide formed after the oxidation of the first polysilicon layer. The extra oxide dip causes the polyoxide to be removed peripherally thus forming a re-entrant cavity along the edge of the floating gate. The re-entrant beak is such that it does not get damaged during the subsequent process steps and is especially suited for cell sizes smaller than 0.35 micrometers.

摘要翻译： 提供了一种用于形成具有尖锐尖峰的分裂栅极闪存单元的方法，其大大改善了单元的编程擦除速度。 通过对第一多晶硅层的氧化后形成的多氧化物进行额外且明智的湿法蚀刻，形成尖锐的喙。 额外的氧化物浸渍导致周围地去除多氧化物，从而沿着浮动栅极的边缘形成重入腔。 再入口的喙使得在后续工艺步骤中不会损坏，特别适用于小于0.35微米的电池尺寸。

公开(公告)号：US5950087A

公开(公告)日：1999-09-07

申请号：US151154

申请日：1998-09-10

申请人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Jaung-Ke Yeh ,  Kuo-Reay Peng ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Jaung-Ke Yeh ,  Kuo-Reay Peng ,  Di-Son Kuo

IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L29/423

CPC分类号： H01L27/11521 ,  H01L29/42324 ,  H01L29/66825

摘要： A method is provided for forming a common self-aligned source line in order to reduce the number of surface contacts and at the same time alleviate the field oxide encroachment into the cell area. Thus, the size of the split-gate flash memory is substantially reduced on both accounts. This is accomplished by forming a buffer polysilicon layer over the floating gate to serve as an etch stop to protect the first poly-oxide of the floating gate during the self-aligned source etching.

摘要翻译： 提供了一种用于形成公共自对准源极线以便减少表面接触的数量并同时减轻场氧化物侵入电池区域的方法。 因此，两个帐户都显着减少了分闸门闪存的大小。 这通过在浮置栅极上形成缓冲多晶硅层来实现，以在自对准源蚀刻期间用作蚀刻停止层以保护浮置栅极的第一多晶氧化物。

公开(公告)号：US5146426A

公开(公告)日：1992-09-08

申请号：US610598

申请日：1990-11-08

申请人： Satyendranath Mukherjee ,  Len-Yuan Tsou ,  Di-Son Kuo

发明人： Satyendranath Mukherjee ,  Len-Yuan Tsou ,  Di-Son Kuo

IPC分类号： G11C17/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/115 ,  H01L29/7885

摘要： An Erasable and Programmable Read Only Memory (EEPROM) cell is provided with an insulated control gate and an insulating floating gate formed in a trench in a semiconductor body. A surface-adjoining drain region is provided alongside an upper portion of a sidewall of the trench, while a source region is provided alongside a lower portion of the trench sidewall, with a channel region extending along the sidewall of the trench between the source and drain regions. The EEPROM cell is programmed by hot electron injection through the sidewall of the trench alongside the channel region, and is erased by Fowler Nordhiem tunneling through a corner region in the bottom of the trench by creating a localized high electric field density in the corner region. In this manner, a highly compact, efficient and durable EEPROM cell is obtained.

公开(公告)号：US20050207264A1

公开(公告)日：2005-09-22

申请号：US11122726

申请日：2005-05-05

申请人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Di-Son Kuo ,  Hung-Cheng Sung ,  Jack Yeh

发明人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Di-Son Kuo ,  Hung-Cheng Sung ,  Jack Yeh

IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7885

摘要： A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, then filling with an isolation oxide and then etching the latter to form a three-dimensional coupling region in the upper portion of the trench. A floating gate is next formed by first filling the three-dimensional region of the trench with polysilicon and etching it. The control gate is formed over the floating gate with an intervening inter-poly oxide. The floating gate forms legs extending into the three-dimensional coupling region of the trench thereby providing a three-dimensional coupling with the source which also assumes a three-dimensional region. The leg or the side-wall of the floating gate forming the third dimension provides the extra area through which coupling between the source and the floating gate is increased. In this manner, a higher coupling ratio is achieved without an increase in the cell size while at the same time alleviating the punchthrough and junction break-down of source region by sharing gate voltage along the side-wall.

摘要翻译： 提供具有能够与电池的浮动栅极三维耦合的三维源的分裂栅极闪存单元及其形成方法。 这是通过首先形成隔离沟槽，用共形氧化物衬里，然后用隔离氧化物填充，然后对其进行蚀刻，以在沟槽的上部形成三维耦合区域。 接下来通过用多晶硅填充沟槽的三维区域并对其进行蚀刻来形成浮栅。 控制栅极通过中间多晶硅氧化物形成在浮动栅上。 浮栅形成延伸到沟槽的三维耦合区域中的支腿，从而提供与源也呈三维区域的三维耦合。 形成第三维的浮动栅的腿或侧壁提供了增加源极和浮动栅极之间的耦合的额外区域。 以这种方式，在不增加电池尺寸的同时实现更高的耦合比，同时通过沿着侧壁共享栅极电压来减轻源极区域的穿通和结断流。

公开(公告)号：US06724036B1

公开(公告)日：2004-04-20

申请号：US09654776

申请日：2000-09-05

申请人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Yai-Fen Lin ,  Chrong Jung Lin ,  Jong Chen ,  Hung-Der Su

发明人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Yai-Fen Lin ,  Chrong Jung Lin ,  Jong Chen ,  Hung-Der Su

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L21/76224 ,  H01L27/115

摘要： A stacked-gate flash memory cell having a shallow trench isolation with a high-step of oxide and high lateral coupling is described. An unconventionally high isolation oxide layer is formed in a shallow trench isolation (STI) in a substrate. The deep opening in the space between the STIs is conformally lined with a polysilicon to form a floating gate extending above the opening. A conformal intergate oxide lines the entire floating gate. A layer of polysilicon overlays the intergate oxide and protrudes downward into the openings to form a control gate with increased coupling to the floating gate.

摘要翻译： 描述了具有高阶氧化物和高横向耦合的浅沟槽隔离的堆叠栅极闪存单元。 在衬底中的浅沟槽隔离（STI）中形成非常规的高隔离氧化层。 在STI之间的空间中的深开口共形地衬有多晶硅以形成在开口上方延伸的浮动栅极。 保形隔离层氧化物对整个浮动栅线进行排列。 一层多晶硅覆盖了间隔栅极氧化物并向下突出到开口中，以形成一个与浮动栅极增加耦合的控制栅极。

公开(公告)号：US06674118B2

公开(公告)日：2004-01-06

申请号：US09876596

申请日：2001-06-08

申请人： Chung-Ker Yeh ,  Hung-Cheng Sung ,  Di-Son Kuo ,  Chia-Ta Hsieh ,  Yai-Fen Lin

发明人： Chung-Ker Yeh ,  Hung-Cheng Sung ,  Di-Son Kuo ,  Chia-Ta Hsieh ,  Yai-Fen Lin

IPC分类号： H01L29788

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11531

摘要： A PIP (Poly-Interpoly-Poly) capacitor with high capacitance is provided in a split-gate flash memory cell. A method is also disclosed to form the same PIP capacitor where the bottom and top plates of the capacitor are formed simultaneously with the floating gate and control gate, respectively, of the split-gate flash memory cell. Furthermore, the thin interpoly oxide of the cell, rather than the thick poly-oxide over the floating gate is used as the insulator between the plates of the capacitor. The resulting capacitor yields high storage capacity through high capacitance per unit area.

摘要翻译： 在分闸式闪存单元中提供了具有高电容的PIP（Poly-Poly Poly Poly-Poly）电容器。 还公开了一种形成相同的PIP电容器的方法，其中电容器的底板和顶板分别与分闸器闪存单元的浮置栅极和控制栅极同时形成。 此外，电池的薄的多晶硅氧化物，而不是浮栅上的厚多晶氧化物，被用作电容器板之间的绝缘体。 所产生的电容通过每单位面积的高电容产生高存储容量。

公开(公告)号：US06509603B2

公开(公告)日：2003-01-21

申请号：US09818296

申请日：2001-03-27

申请人： Yai-Fen Lin ,  Shiou-Hann Liaw ,  Di-Son Kuo ,  Juang-Ke Yeh

发明人： Yai-Fen Lin ,  Shiou-Hann Liaw ,  Di-Son Kuo ,  Juang-Ke Yeh

IPC分类号： H01L29788

CPC分类号： H01L29/42324 ,  H01L29/7885

摘要： A flash EEPROM or split gate flash EEPROM is made on a doped silicon semiconductor N-well formed in a doped semiconductor substrate. A channel with a given width is formed in the N-well which is covered with a tunnel oxide layer, and an N+ doped polysilicon floating gate electrode layer, which can be patterned into a split gate floating gate electrode having a narrower width than the channel width. An interelectrode dielectric layer is formed over the floating gate electrode and the exposed tunnel oxide. A control gate electrode includes a layer composed of P+ doped polysilicon over the interelectrode dielectric layer. The tunnel oxide layer, the floating gate electrode layer, the interelectrode dielectric layer, and the control gate electrode are patterned into a gate electrode stack above the channel. A source region and a drain region are formed in the surface of the substrate with a P type of dopant, the source region and the drain region being self-aligned with the gate electrode stack.

摘要翻译： 在掺杂半导体衬底中形成的掺杂硅半导体N阱上制造闪存EEPROM或分离栅极快速EEPROM。 具有给定宽度的通道形成在被隧道氧化物层覆盖的N阱中，以及N +掺杂多晶硅浮栅电极层，其可以被图案化成具有比沟道窄的宽度的分离栅极浮栅 宽度。 在浮栅电极和暴露的隧道氧化物之上形成电极间电介质层。 控制栅电极包括由电极间电介质层上的P +掺杂多晶硅构成的层。 将隧道氧化物层，浮栅电极层，电极间电介质层和控制栅电极图案化成沟道上方的栅电极堆叠。 源极区域和漏极区域用P型掺杂剂形成在衬底的表面中，源极区域和漏极区域与栅电极堆叠自对准。

公开(公告)号：US06495880B2

公开(公告)日：2002-12-17

申请号：US09760309

申请日：2001-01-16

申请人： Chrong Jung Lin ,  Jong Chen ,  Hung-Der Su ,  Di-Son Kuo

发明人： Chrong Jung Lin ,  Jong Chen ,  Hung-Der Su ,  Di-Son Kuo

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L29/66825

摘要： A new method of fabricating a stacked gate Flash EEPROM device having an improved stacked gate topology is described. Isolation regions are formed on and in a semiconductor substrate. A tunneling oxide layer is provided on the surface of the semiconductor substrate. A first polysilicon layer is deposited overlying the tunneling oxide layer. The first polysilicon layer is polished away until the top surface of the polysilicon is flat and parallel to the top surface of the semiconductor substrate. The first polysilicon layer is etched away to form the floating gate. The source and drain regions are formed within the semiconductor substrate. An interpoly dielectric layer is deposited overlying the first polysilicon layer. A second polysilicon layer is deposited overlying the interpoly dielectric layer. The second polysilicon layer and the interpoly dielectric layer are etched away to form a control gate overlying the floating gate. An insulating layer is deposited overlying the oxide layer and the control gate. Contact openings are formed through the insulating layer to the underlying control gate and to the underlying source and drain regions. The contact openings are filled with a conducting layer to complete the fabrication of the Flash EEPROM device.

摘要翻译： 描述了一种制造具有改进的堆叠栅极拓扑的堆叠栅极闪存EEPROM器件的新方法。 在半导体衬底上形成隔离区。 隧道氧化物层设置在半导体衬底的表面上。 沉积在隧道氧化物层上的第一多晶硅层。 将第一多晶硅层抛光直到多晶硅的顶表面平坦并平行于半导体衬底的顶表面。 蚀刻掉第一多晶硅层以形成浮栅。 源极和漏极区域形成在半导体衬底内。 沉积在第一多晶硅层上的多层介电层。 第二多晶硅层沉积在叠层电介质层上。 蚀刻掉第二多晶硅层和互聚电介质层以形成覆盖浮栅的控制栅极。 绝缘层沉积在氧化层和控制栅上。 通过绝缘层到底层的控制栅极和底层的源极和漏极区域形成接触开口。 接触开口填充有导电层以完成闪速EEPROM装置的制造。

公开(公告)号：US06479859B2

公开(公告)日：2002-11-12

申请号：US09777303

申请日：2001-02-06

申请人： Chia-Ta Hsieh ,  Tai-Fen Lin ,  Wen-Ting Chu ,  Chuang-Ke Yeh ,  Hung-Cheng Sung ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Tai-Fen Lin ,  Wen-Ting Chu ,  Chuang-Ke Yeh ,  Hung-Cheng Sung ,  Di-Son Kuo

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

摘要： A method is disclosed for forming a split-gate flash memory cell where the floating gate of the cell is self-aligned to isolation, to source and to word line. This multi-self-aligned structure, which provides the maximum shrinkage of the cell that is possible, is also disclosed. The multi-self-alignment is accomplished by first defining the floating gate at the same time the trench isolation is formed, and then self-aligning the source to the floating gate by using a nitride layer as a hard mask in place of the traditional polyoxide, and finally forming a polysilicon spacer to align the word line to the floating gate. Furthermore, a thin floating gate is used to form a thin and sharp poly tip through the use of a “smiling effect” to advantage. The tip substantially decreases the coupling ratio of the floating gate to the word line for fast erasing speed, while at the same time increasing the coupling of the source to the floating gate with the attendant increase in the programming speed of the split gate flash memory cell.

摘要翻译： 公开了一种用于形成分离栅闪存单元的方法，其中单元的浮置栅极自对准到隔离，源极和字线。 还公开了提供可能的电池的最大收缩率的多自对准结构。 通过首先在形成沟槽隔离的同时首先定义浮栅，然后通过使用氮化物层作为硬掩模来代替传统的多晶氧体来将源自对准到浮栅来实现多自对准 ，并最终形成多晶硅间隔物以将字线对准浮动栅极。 此外，通过使用“微笑效果”，薄的浮动门用于形成薄而尖的多头尖端。 尖端大大降低了浮动栅极与字线的耦合比，以实现快速擦除速度，同时增加了源极与浮栅的耦合，伴随着分流栅闪存单元的编程速度的增加 。