公开(公告)号：US20090279360A1

公开(公告)日：2009-11-12

申请号：US12387771

申请日：2009-05-07

Applicant: Peter Wung Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

Inventor： Peter Wung Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

IPC: G11C16/04 ,  G11C16/06 ,  H01L21/00

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/30 ,  G11C2211/5641 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  Y10T29/41

Abstract: A NOR flash nonvolatile memory device provides the memory cell size and a low current program process of a NAND flash nonvolatile memory device and the fast, asynchronous random access of a NOR flash nonvolatile memory device. The NOR flash nonvolatile memory device has an array of NOR flash nonvolatile memory circuits. Each NOR flash nonvolatile memory circuit includes a plurality of charge retaining transistors serially connected in a NAND string. A drain of a topmost charge retaining transistor is connected to a bit line associated with the serially connected charge retaining transistors and a source of a bottommost charge retaining transistor is connected to a source line associated with the charge retaining transistors. Each control gate of the charge retaining transistors on each row is commonly connected to a word line. The charge retaining transistors are programmed and erased with a Fowler-Nordheim tunneling process.

Abstract translation: NOR闪存非易失性存储器件提供NAND闪存非易失性存储器件的存储单元尺寸和低电流程序处理以及NOR非易失性存储器件的快速，异步随机存取。 NOR闪存非易失性存储器件具有NOR闪存非易失性存储器电路阵列。 每个NOR非易失性存储器电路包括以NAND串串联连接的多个电荷保持晶体管。 最高电荷保持晶体管的漏极连接到与串联连接的电荷保持晶体管相关联的位线，并且最下面的电荷保持晶体管的源极连接到与电荷保持晶体管相关联的源极线。 每行上的电荷保持晶体管的每个控制栅极共同连接到字线。 电荷保持晶体管通过Fowler-Nordheim隧道工艺进行编程和擦除。

公开(公告)号：US20090119398A1

公开(公告)日：2009-05-07

申请号：US12352207

申请日：2009-01-12

Applicant: Yung-Fu Chang ,  Trey Wafer

Inventor： Yung-Fu Chang ,  Trey Wafer

IPC: G06F15/173

CPC classification number: H04L41/00

Abstract: Embodiments of the invention provide a system and method for automatically managing a network port based on a calendar function. In one embodiment, a discovery protocol is provided for automatically discovering at least one port of at least one switch in a network. Furthermore, a management protocol is provided. The management protocol is configured to automatically manage the at least one port of the at least one switch in the network based on a programmable calendar function. In addition, a reconfiguration protocol is also provided. The reconfiguration protocol is configured to reconfigure the calendar function of the automatic management of the at least one port of the at least one switch in the network.

Abstract translation: 本发明的实施例提供了一种基于日历功能来自动管理网络端口的系统和方法。 在一个实施例中，提供发现协议以自动发现网络中的至少一个交换机的至少一个端口。 此外，还提供管理协议。 管理协议被配置为基于可编程日历功能来自动管理网络中的至少一个交换机的至少一个端口。 此外，还提供了重新配置协议。 重新配置协议被配置为重新配置网络中的至少一个交换机的至少一个端口的自动管理的日历功能。

公开(公告)号：US20080205141A1

公开(公告)日：2008-08-28

申请号：US12069637

申请日：2008-02-12

Applicant: Peter Lee ,  Fu-Chang Hsu

Inventor： Peter Lee ,  Fu-Chang Hsu

IPC: G11C16/04 ,  G11C16/06

CPC classification number: H01L29/7887 ,  G11C7/18 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  H01L27/115 ,  H01L29/7923

Abstract: A control apparatus programs, reads, and erases trapped charges representing multiple data bits from a charge trapping region of a NMOS dual-sided charge-trapping nonvolatile memory cell includes a programming circuit, an erasing circuit, and a reading circuit. The programming circuit provides a negative medium large program voltage to cell's gate along with positive drain and source voltage to inject hot carriers of holes to two charge trapping regions, one of a plurality of threshold adjustment voltages representing a portion of the multiple data bits to the drain and source regions to set the hot carrier charge levels to the two charge trapping regions. The erasing circuit provides a very large positive erase voltage to tunnel the electrons from cell's channel to whole trapping layer including the two charge trapping regions. The reading circuit generates one of a plurality of threshold detection voltages to detect one of a plurality of programmed threshold voltages representative of multiple data bits, generates a drain voltage level to activate the charge-trapping nonvolatile memory cell.

Abstract translation: 控制装置对来自NMOS双侧电荷捕获非易失性存储单元的电荷捕获区域的多个数据位进行编程，读取和擦除捕获的电荷包括编程电路，擦除电路和读取电路。 编程电路向单元的栅极提供负的中等大的编程电压以及正的漏极和源极电压，以将空穴的热载流子注入到两个电荷俘获区域，多个阈值调整电压中的一个表示多个数据位的一部分 漏极和源极区域，以将热载流子电荷电平设置为两个电荷捕获区域。 擦除电路提供非常大的正擦除电压，以将电子从电池的通道隧穿到包括两个电荷俘获区域的整个俘获层。 读取电路产生多个阈值检测电压中的一个，以检测表示多个数据位的多个编程的阈值电压中的一个，产生漏极电压电平以激活电荷捕获非易失性存储单元。

公开(公告)号：US20080205140A1

公开(公告)日：2008-08-28

申请号：US12069228

申请日：2008-02-08

Applicant: Peter Lee ,  Fu-Chang Hsu

Inventor： Peter Lee ,  Fu-Chang Hsu

IPC: G11C16/04 ,  G11C16/06 ,  H01L21/336

CPC classification number: H01L29/7887 ,  G11C7/18 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  H01L27/115 ,  H01L29/7923

Abstract: A nonvolatile memory array includes a plurality of dual-sided charge-trapping nonvolatile memory cells arranged in rows and columns. The dual-sided charge-trapping nonvolatile memory cells on each column form at least one grouping that is arranged in a NAND series string of dual-sided charge-trapping nonvolatile memory cells. Each NAND series string has a top select transistor and a bottom select transistor. A plurality of bit lines is connected in a cross connective columnar bit line structure such that each column of the dual-sided charge-trapping nonvolatile memory cells is connected to an associated pair of bit lines. The first of the associated pair of bit lines is further connected to a first adjacent column of dual-sided charge-trapping nonvolatile memory cells and the second of the associated pair of bit lines is further associated with a second adjacent column of the dual-sided charge-trapping nonvolatile memory cells.

Abstract translation: 非易失性存储器阵列包括以行和列排列的多个双面电荷俘获非易失性存储单元。 每列上的双面电荷捕获非易失性存储单元形成至少一个分组，其被布置在NAND串联的双面电荷捕获非易失性存储单元中。 每个NAND串联串具有顶部选择晶体管和底部选择晶体管。 多个位线连接在交叉连接柱状位线结构中，使得双面电荷捕获非易失性存储器单元的每一列连接到相关的一对位线。 相关联的一对位线中的第一个进一步连接到双面电荷捕获非易失性存储器单元的第一相邻列，并且相关联的位线对中的第二相关联还与双面电荷捕获非易失性存储器单元的第二相邻列相关联 电荷捕获非易失性存储单元。

公开(公告)号：US20080166904A1

公开(公告)日：2008-07-10

申请号：US12076143

申请日：2008-03-14

Applicant: Hsien-Chung Ou ,  Chen-Fu Chang ,  Li-Li Yang

Inventor： Hsien-Chung Ou ,  Chen-Fu Chang ,  Li-Li Yang

IPC: H01R3/00

CPC classification number: H01R35/02

Abstract: A flexible cable for an optical disk drive is disposed at a case comprising an upper case and a lower case. The flexible cable comprises a fastening part fixed at the lower case and a moving part extended in the reverse direction of one end of the fastening part to form a beginning end fixed at the case. An intensive area comprised of elastic material is disposed at the surface of the beginning end and nearby the beginning end of the moving part. A smooth layer is disposed at the inside of the upper case and located on the moving path of the intensive area disposed at the moving part to be touched by the intensive area when the moving part is bent reversely. A secondary intensive area is disposed at the moving part, and is extended or separated from the intensive area, to prevent the flexible cable drooping.

Abstract translation: 用于光盘驱动器的柔性电缆设置在包括上壳体和下壳体的壳体上。 柔性电缆包括固定在下壳体上的紧固部分和沿紧固部分一端的相反方向延伸的移动部件，以形成固定在壳体上的起始端。 由弹性材料构成的密集区域设置在起始端的表面和移动部件的开始端附近。 当移动部分被反向弯曲时，平滑层设置在上壳体的内部并且位于设置在移动部分处的集中区域的移动路径上以便被密集区域接触。 二次密集区域设置在移动部分处，并且从密集区域延伸或分离，以防止柔性电缆下垂。

公开(公告)号：US07349257B2

公开(公告)日：2008-03-25

申请号：US11633334

申请日：2006-12-04

Applicant: Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma

Inventor： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma

IPC: G11C11/34

CPC classification number: H01L27/115 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/14 ,  G11C16/16 ,  G11C16/3445 ,  G11C2216/18 ,  G11C2216/22 ,  H01L27/11521 ,  H01L27/11524

Abstract: A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accommodate the bit line pitch of the Flash cell, which facilitates combining the two memories into memory banks containing both cells. The EEPROM cells are erased by byte while the Flash cells erased by block. The small select transistor has a small channel length and width, which is compensated by increasing gate voltages on the select transistor and pre-charge bitline during CHE program operation.

Abstract translation: 描述了组合EEPROM和闪存，其中包含单元，其中闪存单元的堆叠栅极晶体管与选择晶体管结合使用以形成EEPROM单元。 使选择晶体管足够小，以便允许EEPROM单元适应闪存单元的位线间距，这有助于将两个存储器组合成包含两个单元的存储体。 闪存单元被块擦除时，EEPROM单元被字节擦除。 小选择晶体管具有小的沟道长度和宽度，其通过在CHE编程操作期间增加选择晶体管上的栅极电压和预充电位线来补偿。

公开(公告)号：US07339824B2

公开(公告)日：2008-03-04

申请号：US11633326

申请日：2006-12-04

Applicant: Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma

Inventor： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma

IPC: G11C16/04

CPC classification number: H01L27/115 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/14 ,  G11C16/16 ,  G11C16/3445 ,  G11C2216/18 ,  G11C2216/22 ,  H01L27/11521 ,  H01L27/11524

Abstract: A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accommodate the bit line pitch of the Flash cell, which facilitates combining the two memories into memory banks containing both cells. The EEPROM cells are erased by byte while the Flash cells erased by block. The small select transistor has a small channel length and width, which is compensated by increasing gate voltages on the select transistor and pre-charge bitline during CHE program operation.

公开(公告)号：US07324384B2

公开(公告)日：2008-01-29

申请号：US11442379

申请日：2006-05-26

Applicant: Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma ,  Koucheng Wu

Inventor： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma ,  Koucheng Wu

IPC: G11C16/06

CPC classification number: H01L27/115 ,  G11C11/005 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3436 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

Abstract: A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.

Abstract translation: 公开了一种新颖的基于FLASH的EEPROM单元，解码器和布局方案，以消除单元阵列中的面积消耗的划分三阱，并允许字节擦除和字节程序用于高P / E周期。 此外，用于EEPROM部件的处理兼容FLASH单元可以与FLASH和ROM部件集成，从而实现了优异的组合，单片，非易失性存储器。 与所有以前的技术不同，ROM，EEPROM和FLASH本发明的新颖的组合非易失性存储器或任何两个的组合由一个统一的，完全兼容的，高度可扩展的BN +单元和统一过程组成。 此外，其单元操作方案在P / E操作期间具有零阵列开销和零扰动。 该新颖的组合非易失性存储器旨在满足那些需要灵活的写入大小（以字节，页面和块为单位）以低成本的市场的需求。

公开(公告)号：US07314667B2

公开(公告)日：2008-01-01

申请号：US10799435

申请日：2004-03-12

Applicant: Alexander Tregub ,  Florence Eschbach ,  Fu-Chang Lo ,  Susan M. Holl

Inventor： Alexander Tregub ,  Florence Eschbach ,  Fu-Chang Lo ,  Susan M. Holl

IPC: B32B27/16 ,  B32B27/28

CPC classification number: G03F1/62 ,  Y10T428/3154 ,  Y10T428/31544

Abstract: Disclosed are pellicle compositions and methods of making such pellicle compositions. The pellicle compositions provided include highly fluorinated polymers as well as fluorinated polymer/PVDF co-polymers.

Abstract translation: 公开了防护薄膜组合物和制备这种防护薄膜组合物的方法。 所提供的防护薄膜组合物包括高度氟化的聚合物以及氟化聚合物/ PVDF共聚物。

公开(公告)号：US20070296216A1

公开(公告)日：2007-12-27

申请号：US11812262

申请日：2007-06-15

Applicant: Fu-Chang Liao

Inventor： Fu-Chang Liao

IPC: F01D15/10

CPC classification number: F03D3/005 ,  F03D3/062 ,  Y02E10/74

Abstract: A wind generator has a post, a rail mounted on the post and a blade assembly mounted rotatably on a top of the post. The blade assembly includes multiple blades radially formed around a base. Each blade has multiple vents, a slat and multiple relief valves. The slat is controllable mounted to open or close the vents, so as to adjust a force of wind applied to the blades. The relief valves are mounted pivotally to selectively cover valve holes formed through the blades to prevent the wind resistance force applied to the blades. Therefore, the wind generator can work in both turbulent and with a low wind force without breaking.

Abstract translation: 风力发电机具有柱，安装在柱上的导轨和可旋转地安装在柱的顶部上的叶片组件。 叶片组件包括围绕基部径向地形成的多个叶片。 每个叶片具有多个通风口，一个板条和多个安全阀。 板条可控制地安装以打开或关闭通风口，以便调节施加到叶片的风力。 安全阀枢转地安装以选择性地覆盖通过叶片形成的阀孔，以防止施加到叶片的抗风力。 因此，风力发电机可以在湍流和低风力下工作而不破裂。