公开(公告)号：US07319425B2

公开(公告)日：2008-01-15

申请号：US11343064

申请日：2006-01-30

Applicant: John K. Fiorenza ,  Todd Sepke ,  Hae-Seung Lee ,  Charles G. Sodini

Inventor： John K. Fiorenza ,  Todd Sepke ,  Hae-Seung Lee ,  Charles G. Sodini

IPC: H03M1/12

CPC classification number: H03M1/38 ,  H03F3/005

Abstract: Described is a switched capacitor circuit for performing an analog circuit function. Unlike conventional switched capacitor circuits employing operational amplifiers, the switched capacitor circuit uses a comparator and does not require direct feedback between the input and output of the comparator. The switched capacitor circuit includes a first and a second switched capacitance network, a comparator and a current source. The first switched capacitance network has an input terminal to receive a circuit input voltage during a first phase. The comparator has an input terminal in communication with the first switched capacitance network and an output terminal in communication with the second switched capacitance network through a switched terminal. The current source communicates with the switched capacitance networks and supplies a current to charge the networks during a second phase. The circuit can be used, for example, to provide high gain amplification in integrated circuits.

Abstract translation: 描述了用于执行模拟电路功能的开关电容器电路。 与使用运算放大器的传统开关电容器电路不同，开关电容器电路使用比较器，并且不需要比较器的输入和输出之间的直接反馈。 开关电容电路包括第一和第二开关电容网络，比较器和电流源。 第一开关电容网络具有用于在第一阶段期间接收电路输入电压的输入端子。 比较器具有与第一开关电容网络通信的输入端子和通过开关端子与第二开关电容网络通信的输出端子。 电流源与开关电容网络通信，并在第二阶段提供电流来对网络充电。 该电路可以用于例如在集成电路中提供高增益放大。

公开(公告)号：US07242429B1

公开(公告)日：2007-07-10

申请号：US10335677

申请日：2003-01-02

Applicant: Hae-Seung Lee ,  Keith Glen Fife

Inventor： Hae-Seung Lee ,  Keith Glen Fife

IPC: H04N3/14 ,  H04N5/335

CPC classification number: H04N5/3745 ,  H04N5/3575 ,  H04N5/361

Abstract: A method for determining a pixel output value of an imager; the imager having a plurality of pixels, a reset switch associated with each pixel and a select switch associated with each pixel; due to incident illumination upon a pixel of the imager after a reset period. The method captures a first pixel output value when the reset switch is OFF during a reset period and the select switch is ON during a reset period and captures a second pixel output value when the select switch is ON near an end of an integration period. If the second pixel output value is captured when the select switch is ON near an end of a first integration period, the first pixel output value may be captured when the reset switch is OFF during a reset period preceding the first integration period and the select switch is ON during a reset period preceding the first integration period. Moreover, if the second pixel output value is captured when the select switch is ON near an end of a first integration period, the first pixel output value may be captured when the reset switch is OFF during a reset period immediately following the first integration period and the select switch is ON during a reset period immediately following the first integration period.

Abstract translation: 一种用于确定成像器的像素输出值的方法; 成像器具有多个像素，与每个像素相关联的复位开关和与每个像素相关联的选择开关; 由于在复位周期之后对成像器的像素的入射照明。 该方法在复位期间复位开关为OFF时在复位期间捕获第一像素输出值，并且在复位期间选择开关为ON，并且当积分周期结束时选择开关接通时捕获第二像素输出值。 如果在第一积分周期结束时选择开关接通时捕获第二像素输出值，则可以在第一积分期间的复位期间和选择开关之间的复位开关为OFF时捕获第一像素输出值 在第一积分期间之前的复位期间为ON。 此外，如果在第一积分周期结束时选择开关接通时捕获第二像素输出值，则在紧接着第一积分周期之后的复位周期期间当复位开关为OFF时可以捕获第一像素输出值;以及 在第一积分期间之后的复位期间，选择开关为ON。

公开(公告)号：US20070001518A1

公开(公告)日：2007-01-04

申请号：US11454435

申请日：2006-06-16

Applicant: Hae-Seung Lee

Inventor： Hae-Seung Lee

IPC: B23K11/24

CPC classification number: G11C27/024 ,  H03H19/004 ,  Y10T307/74

Abstract: A sampled-data analog circuit includes a level-crossing detector. The level-crossing detector controls sampling switches to provide a precise sample of the output voltage when the level-crossing detector senses the predetermined level crossing of the input signal. The level-crossing detection may be a zero-crossing detection. An optional common-mode feedback circuit can keep the output common-mode voltage substantially constant.

公开(公告)号：US06891322B2

公开(公告)日：2005-05-10

申请号：US10053553

申请日：2002-01-24

Applicant: Jong-Hyuk Lee ,  Yoon-hyung Cho ,  Hae-Seung Lee ,  Dong-Sik Zang ,  Jung-Hwan Park

Inventor： Jong-Hyuk Lee ,  Yoon-hyung Cho ,  Hae-Seung Lee ,  Dong-Sik Zang ,  Jung-Hwan Park

IPC: G02B5/22 ,  G09F9/00 ,  G09F9/30 ,  H01J9/20 ,  H01J11/12 ,  H01J11/24 ,  H01J11/26 ,  H01J11/44 ,  H01J29/18 ,  H01J29/28 ,  H01J29/32 ,  H01J29/88 ,  H01J29/89 ,  H01J29/30 ,  H01J61/40

CPC classification number: H01J29/327 ,  H01J29/185 ,  H01J29/89 ,  H01J2229/8916

Abstract: A filter layer for a display and a method of preparing the filter layer, and a display including the filter layer, are provided. The filter layer for a display includes oxide particles and nano-sized metal particulates adhered to the surface of the oxide particles. A surface plasma resonance (SPR) phenomenon is triggered at the interface of the oxide/metal to selectively absorb light of at least one predetermined wavelength.

Abstract translation: 提供了一种用于显示器的过滤层及其制备方法，以及包括该过滤层的显示器。 用于显示器的过滤层包括粘附到氧化物颗粒表面的氧化物颗粒和纳米尺寸的金属颗粒。 在氧化物/金属的界面处触发表面等离子体共振（SPR）现象，以选择性地吸收至少一个预定波长的光。

公开(公告)号：US06600471B2

公开(公告)日：2003-07-29

申请号：US09916822

申请日：2001-07-27

Applicant: Hae-Seung Lee ,  Charles G. Sodini ,  Keith G. Fife

Inventor： Hae-Seung Lee ,  Charles G. Sodini ,  Keith G. Fife

IPC: G09G336

CPC classification number: H04N5/3765 ,  H04N5/35527 ,  H04N5/3577 ,  H04N5/374

Abstract: There is provided an imaging system including a MOS pixel array having a number, r, of rows of pixels. Each pixel of the array includes a light detecting element, a reset node connected to the light detecting element for controlling dissipation of photogenerated charge produced by the light detecting element, and a sense node connected to the light detecting element for measuring photogenerated charge produced by the light detecting element. A charge control voltage generation circuit is provided, having a topology for producing a plurality of charge control voltages selected to control dissipation of photogenerated charge produced by the light detecting element, in accordance with a corresponding pixel transfer function. A switch circuit is connected to the voltage generation circuit and to the pixel array to apply voltages produced by the charge control voltage generation circuit to reset nodes of pixels. The application by the switch circuit of each of the charge control voltages to a row of pixel reset nodes is characterized by a voltage application settling time, tS, that is less than about 1/Nrf, where N is an integer and f is imager frame rate. This provides the ability to implement a desired transfer function, to expand imager dynamic range, in a manner that is immune to capacitances of the imager, by causing the voltage spikes, or glitches, associated with imager row capacitance, to decay substantially completely during the time over which an imager pixel row is accessed to apply a control voltage.

公开(公告)号：US06479928B1

公开(公告)日：2002-11-12

申请号：US09577881

申请日：2000-05-25

Applicant: Jong-hyuk Lee ,  Jung-hwan Park ,  Yoon-hyung Cho ,  Hae-seung Lee ,  Dong-sik Zang

Inventor： Jong-hyuk Lee ,  Jung-hwan Park ,  Yoon-hyung Cho ,  Hae-seung Lee ,  Dong-sik Zang

IPC: H04N572

CPC classification number: H01J29/898

Abstract: A CRT has an improved contrast with a provision of a filter layer where nano-sized metal particles are dispersed in a dielectric matrix to selectively absorb light in predetermined wavelengths, specifically wavelengths between peak wavelengths of primary colors emitted by phosphors coated on the inner surface of the face plate. The improved contrast is a result of the metal particles in a dielectric matrix resonating with particular wavelengths and thus absorbing them.

Abstract translation: CRT具有改进的对比度，其中提供过滤层，其中纳米尺寸金属颗粒分散在介质矩阵中以选择性地吸收预定波长的光，特别是在涂覆在内表面上的磷光体发射的原色的峰值波长之间的波长 面板。 改善的对比度是介电矩阵中的金属颗粒与特定波长共振并因此吸收它们的结果。

公开(公告)号：US5223754A

公开(公告)日：1993-06-29

申请号：US628340

申请日：1990-12-14

Applicant: Steve Decker ,  John L. Wyatt, Jr. ,  Hae-Seung Lee

Inventor： Steve Decker ,  John L. Wyatt, Jr. ,  Hae-Seung Lee

IPC: H01L27/088

CPC classification number: H01L27/088

Abstract: A simple transistor circuit which acts as a linear resistor for small applied voltages, but becomes extremely resistive for large applied voltages is disclosed. Two-dimensional resistive grids comprising these resistive fuses can be employed to smooth and segment discretized images in machine vision. Existing and previously proposed VLSI implementations of resistive fuses have required at least thirty-three transistors. The resistive fuse circuit of the present invention uses only four transistors in its simplest embodiment, thus making it possible to design much denser vision arrays.

Abstract translation: 公开了一种简单的晶体管电路，其作为用于小施加电压的线性电阻器，但是对于大的施加电压变得极大的阻力。 可以采用包含这些电阻熔丝的二维电阻栅格来平滑和分段机器视觉中的离散化图像。 电阻式熔断器的现有和先前提出的VLSI实现至少需要三十三个晶体管。 本发明的电阻式熔丝电路在其最简单的实施例中仅使用四个晶体管，从而可以设计出更加密集的视觉阵列。

公开(公告)号：US4860232A

公开(公告)日：1989-08-22

申请号：US41773

申请日：1987-04-22

Applicant: Hae-Seung Lee ,  Roger T. Howe ,  Joseph T. Kung

Inventor： Hae-Seung Lee ,  Roger T. Howe ,  Joseph T. Kung

IPC: G01D5/241 ,  G01L9/12 ,  G01R17/06 ,  G01R27/26

CPC classification number: G01D5/2415 ,  G01L9/125 ,  G01R17/06 ,  G01R27/2605

Abstract: The present invention comprises a circuit for measuring the capacitive differences of small capacitors. The circuit comprises a reference capacitor and a sensor capacitor. Connected to one of the plates of each capacitor is a switch which connects the capacitors to one of two reference voltages. The other plate of the capacitors are connected to an input terminal of a voltage comparator. The comparator compares the input voltage with a third reference voltage. Differences in voltages detected by the comparator are applied to a feedback loop for generating an offset voltage at the input terminal. The offset voltage applied at the input terminal is proportional to the capacitive difference between the reference capacitor and the sensor capacitor. The feedback loop comprises a successive approximation register for digitizing the offset voltages and a digital to analog converter for converting the digitized voltages into analog voltages which are applied at the input terminal. Digitized offset voltages can be measured at the output of the successive approximation register.

Abstract translation: 本发明包括用于测量小电容器的电容差的电路。 该电路包括参考电容器和传感器电容器。 连接到每个电容器的一个板的是将电容器连接到两个参考电压之一的开关。 电容器的另一个电极连接到电压比较器的输入端。 比较器将输入电压与第三参考电压进行比较。 由比较器检测的电压的差异被施加到用于在输入端产生偏移电压的反馈回路。 施加在输入端子的偏移电压与参考电容器和传感器电容器之间的电容差成正比。 反馈回路包括用于数字化偏移电压的逐次逼近寄存器和用于将数字化电压转换成在输入端施加的模拟电压的数模转换器。 可以在逐次逼近寄存器的输出端测量数字化偏移电压。

公开(公告)号：US09154089B2

公开(公告)日：2015-10-06

申请号：US14210958

申请日：2014-03-14

Applicant: Hae-Seung Lee

Inventor： Hae-Seung Lee

IPC: H03F3/16 ,  G11C27/02 ,  H03H19/00 ,  H03M1/12 ,  G11C13/02 ,  H03F3/00

CPC classification number: H03F3/16 ,  G11C27/024 ,  H03F3/005 ,  H03F3/62 ,  H03F3/70 ,  H03F2200/156 ,  H03F2200/159 ,  H03F2200/357 ,  H03F2200/42 ,  H03H19/004 ,  H03M1/1245 ,  H03M1/468

Abstract: Amplifier circuits implemented with a buffer amplifier with a voltage gain substantially equal to one. In one example, a continuous-time amplifier is implemented by applying the input source across the input and the output terminals of the buffer amplifier. In another example, a discrete-time amplifier is implemented. During the sampling phase at least one input voltage is sampled, and during the transfer phase at least one capacitor is coupled across the input and the output terminals of a buffer amplifier to effectuate an amplification.

Abstract translation: 具有电压增益基本上等于1的缓冲放大器实现的放大器电路。 在一个示例中，通过在缓冲放大器的输入端和输出端上施加输入源来实现连续时间放大器。 在另一示例中，实现了离散时间放大器。 在采样阶段期间，对至少一个输入电压进行采样，并且在传输阶段期间，至少一个电容器跨越缓冲放大器的输入端和输出端耦合以实现放大。

公开(公告)号：US08373489B2

公开(公告)日：2013-02-12

申请号：US12909168

申请日：2010-10-21

Applicant: Hae-Seung Lee

Inventor： Hae-Seung Lee

IPC: G06F7/64

CPC classification number: H03H19/004 ,  G11C7/06 ,  G11C27/026 ,  H03M1/0607 ,  H03M1/403 ,  H03M1/442 ,  H03M3/356

Abstract: A comparator based circuit with effective offset cancellation includes first and second amplifiers and an offset capacitor operatively connected to the first and second amplifiers. An offset voltage source generates an offset voltage. A first switch connects the offset voltage source to ground during a first time period. The first amplifier generates an output voltage in response to the first switch connecting the offset voltage source to ground during the first time period. A second switch connects the offset capacitor to ground during a second time period. The first switch disconnects the offset voltage source from ground during a third time period, and the second switch disconnects the offset capacitor from ground during the third time period.