公开(公告)号：US20150079755A1

公开(公告)日：2015-03-19

申请号：US14559542

申请日：2014-12-03

Applicant: Tzu-Cheng Kao ,  Jian-Hsing Lee ,  Jin-Lian Su ,  Huan-Ping Chu ,  Hung-Der Su

Inventor： Tzu-Cheng Kao ,  Jian-Hsing Lee ,  Jin-Lian Su ,  Huan-Ping Chu ,  Hung-Der Su

IPC: H01L29/66

CPC classification number: H01L29/66681 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: a first conductive type substrate, a second conductive type high voltage well, a gate, a first conductive type body region, a second conductive type source, a second conductive type drain, a first conductive type body electrode, and a first conductive type floating region. The floating region is formed in the body region, which is electrically floating and is electrically isolated from the source and the gate, such that the electrostatic discharge (ESD) effect is mitigated.

Abstract translation: 本发明公开了一种双扩散金属氧化物半导体（DMOS）器件及其制造方法。 DMOS器件包括：第一导电类型衬底，第二导电型高压阱，栅极，第一导电类型体区域，第二导电类型源极，第二导电类型漏极，第一导电型体电极和 第一导电型浮动区域。 浮动区域形成在电气浮动并且与源极和栅极电隔离的体区中，使得减轻静电放电（ESD）效应。

公开(公告)号：US08928078B2

公开(公告)日：2015-01-06

申请号：US13726579

申请日：2012-12-25

Applicant: Tzu-Cheng Kao ,  Jian-Hsing Lee ,  Jin-Lian Su ,  Huan-Ping Chu ,  Hung-Der Su

Inventor： Tzu-Cheng Kao ,  Jian-Hsing Lee ,  Jin-Lian Su ,  Huan-Ping Chu ,  Hung-Der Su

IPC: H01L29/76 ,  H01L29/94 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66681 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: a first conductive type substrate, a second conductive type high voltage well, a gate, a first conductive type body region, a second conductive type source, a second conductive type drain, a first conductive type body electrode, and a first conductive type floating region. The floating region is formed in the body region, which is electrically floating and is electrically isolated from the source and the gate, such that the electrostatic discharge (ESD) effect is mitigated.

Abstract translation: 本发明公开了一种双扩散金属氧化物半导体（DMOS）器件及其制造方法。 DMOS器件包括：第一导电类型衬底，第二导电型高压阱，栅极，第一导电类型体区域，第二导电类型源极，第二导电类型漏极，第一导电型体电极和 第一导电型浮动区域。 浮动区域形成在电气浮动并且与源极和栅极电隔离的体区中，使得减轻静电放电（ESD）效应。

公开(公告)号：US20140175545A1

公开(公告)日：2014-06-26

申请号：US13726579

申请日：2012-12-25

Applicant: Tzu-Cheng Kao ,  Jian-Hsing Lee ,  Jin-Lian Su ,  Huan-Ping Chu ,  Hung-Der Su

Inventor： Tzu-Cheng Kao ,  Jian-Hsing Lee ,  Jin-Lian Su ,  Huan-Ping Chu ,  Hung-Der Su

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66681 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: a first conductive type substrate, a second conductive type high voltage well, a gate, a first conductive type body region, a second conductive type source, a second conductive type drain, a first conductive type body electrode, and a first conductive type floating region. The floating region is formed in the body region, which is electrically floating and is electrically isolated from the source and the gate, such that the electrostatic discharge (ESD) effect is mitigated.

Abstract translation: 本发明公开了一种双扩散金属氧化物半导体（DMOS）器件及其制造方法。 DMOS器件包括：第一导电类型衬底，第二导电型高压阱，栅极，第一导电类型体区域，第二导电类型源极，第二导电类型漏极，第一导电型体电极和 第一导电型浮动区域。 浮动区域形成在电气浮动并且与源极和栅极电隔离的体区中，使得减轻静电放电（ESD）效应。

公开(公告)号：US08194371B2

公开(公告)日：2012-06-05

申请号：US12419608

申请日：2009-04-07

Applicant: Chin-Hsin Tang ,  Jian-Hsing Lee

Inventor： Chin-Hsin Tang ,  Jian-Hsing Lee

IPC: H02H9/00

CPC classification number: H01L27/0207 ,  H01L27/0266 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is provided. In an embodiment, the semiconductor device includes an inverter. The inverter is coupled to an NMOS device. The NMOS device may be protection device which protects the inverter from charging effects and/or plasma induced damage. The NMOS device may be coupled to a power source (e.g., Vss). The NMOS device may be further coupled to a capacitor. The charge of the capacitor may discharge a current through the NMOS device to the power source.

Abstract translation: 提供半导体器件。 在一个实施例中，半导体器件包括反相器。 反相器耦合到NMOS器件。 NMOS器件可以是保护逆变器免受充电效应和/或等离子体引起的损坏的保护装置。 NMOS器件可以耦合到电源（例如，Vss）。 NMOS器件可以进一步耦合到电容器。 电容器的电荷可以将通过NMOS器件的电流放电到电源。

公开(公告)号：US20120069479A1

公开(公告)日：2012-03-22

申请号：US12884588

申请日：2010-09-17

Applicant: Jian-Hsing LEE

Inventor： Jian-Hsing LEE

IPC: H02H9/04

CPC classification number: H01L27/0262

Abstract: The present invention discloses a power transistor device and a low dropout regulator (LDO) with electrostatic discharge protection. The power transistor device includes: a P-type metal oxide semiconductor (PMOS) field effect transistor (FET), having a source and a drain electrically connected to a voltage input terminal and a voltage output terminal respectively; and an electrostatic discharge protection device, electrically connected to the voltage input terminal and the voltage output terminal, for providing an electrostatic discharge path to protect the PMOSFET.

Abstract translation: 本发明公开了一种具有静电放电保护功率晶体管器件和低压差稳压器（LDO）。 功率晶体管器件包括：分别与电压输入端子和电压输出端子电连接的源极和漏极的P型金属氧化物半导体（PMOS）场效应晶体管（FET） 以及电连接到电压输入端子和电压输出端子的静电放电保护装置，用于提供静电放电路径以保护PMOSFET。

公开(公告)号：US20100254050A1

公开(公告)日：2010-10-07

申请号：US12419608

申请日：2009-04-07

Applicant: Chin-Hsin Tang ,  Jian-Hsing Lee

Inventor： Chin-Hsin Tang ,  Jian-Hsing Lee

IPC: H02H9/04 ,  H01L27/06 ,  H01L21/02

CPC classification number: H01L27/0207 ,  H01L27/0266 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is provided. In an embodiment, the semiconductor device includes an inverter. The inverter is coupled to an NMOS device. The NMOS device may be protection device which protects the inverter from charging effects and/or plasma induced damage. The NMOS device may be coupled to a power source (e.g., Vss). The NMOS device may be further coupled to a capacitor. The charge of the capacitor may discharge a current through the NMOS device to the power source.

Abstract translation: 提供半导体器件。 在一个实施例中，半导体器件包括反相器。 反相器耦合到NMOS器件。 NMOS器件可以是保护逆变器免受充电效应和/或等离子体引起的损坏的保护装置。 NMOS器件可以耦合到电源（例如，Vss）。 NMOS器件可以进一步耦合到电容器。 电容器的电荷可以将通过NMOS器件的电流放电到电源。

公开(公告)号：US07781834B2

公开(公告)日：2010-08-24

申请号：US11773364

申请日：2007-07-03

Applicant: Chi-San Wei ,  Kuo-Ming Wu ,  Jian-Hsing Lee

Inventor： Chi-San Wei ,  Kuo-Ming Wu ,  Jian-Hsing Lee

IPC: H01L29/78 ,  H01L29/10

CPC classification number: H01L29/7816 ,  H01L29/0696 ,  H01L29/0878

Abstract: A semiconductor device includes a gate electrode over a semiconductor substrate, wherein the gate electrode has a gate width direction; a source/drain region in the semiconductor substrate and adjacent the gate electrode, wherein the source/drain region has a first width in a direction parallel to the gate width direction; and a bulk pick-up region in the semiconductor substrate and abutting the source/drain region. The bulk pick-up region and the source/drain region have opposite conductivity types. The bulk pick-up region has a second width in the width direction, and wherein the second width is substantially less than the first width.

Abstract translation: 半导体器件包括在半导体衬底上的栅电极，其中栅电极具有栅极宽度方向; 在所述半导体衬底中并且与所述栅电极相邻的源极/漏极区域，其中所述源极/漏极区域在平行于所述栅极宽度方向的方向上具有第一宽度; 以及半导体衬底中的块体拾取区域并且邻接源极/漏极区域。 本体拾取区域和源极/漏极区域具有相反的导电类型。 本体拾取区域在宽度方向上具有第二宽度，并且其中第二宽度基本上小于第一宽度。

公开(公告)号：US07663851B2

公开(公告)日：2010-02-16

申请号：US11137265

申请日：2005-05-25

Applicant: Shao-Chang Huang ,  Jian-Hsing Lee

Inventor： Shao-Chang Huang ,  Jian-Hsing Lee

IPC: H02H9/00 ,  H02H3/20 ,  H02H9/04 ,  H02H3/22

CPC classification number: H01L27/0251

Abstract: The present invention discloses a tie-off circuit coupled between a first potential and a gate of a MOS device whose source is connected to a second potential. The tie-off circuit includes at least one resistor and at least on diode. The resistor is coupled between the gate of the MOS device and the first potential for preventing the gate of the MOS device from floating during a normal circuit operation. The diode is coupled between the gate of the MOS device and the first potential, in parallel with the resistor, for reducing a voltage difference across a gate oxide layer of the MOS device during an electrostatic discharge (ESD) event, thereby protecting the same from ESD damage.

Abstract translation: 本发明公开了一种耦合在源极连接到第二电位的MOS器件的第一电位和栅极之间的断开电路。 连接电路至少包括一个电阻器，并且至少在二极管上。 电阻器耦合在MOS器件的栅极和用于防止MOS器件的栅极在正常电路操作期间浮置的第一电位之间。 二极管耦合在MOS器件的栅极和与电阻器并联的第一电位之间，用于在静电放电（ESD）事件期间减小MOS器件的栅氧化层上的电压差，从而保护 ESD损坏。

公开(公告)号：US20100013016A1

公开(公告)日：2010-01-21

申请号：US12176166

申请日：2008-07-18

Applicant: Jiaw-Ren Shih ,  Jian-Hsing Lee

Inventor： Jiaw-Ren Shih ,  Jian-Hsing Lee

IPC: H02H9/04 ,  H01L27/06

CPC classification number: H01L27/0259 ,  H01L27/1203

Abstract: An electrostatic discharge (ESD) protection circuit includes a buried oxide layer; a semiconductor layer on the buried oxide layer; and a first and a second MOS device. The first MOS device includes a first gate over the semiconductor layer; a first well region having a portion underlying the first gate; and a first source region and a first drain region in the semiconductor layer. The second MOS device includes a second gate over the semiconductor layer; and a second well region having a portion underlying the first gate. The second well region is connected to a discharging node. The first well region is connected to the discharging node through the second well region, and is not directly connected to the discharging node. The second MOS device further includes a second source region and a second drain region in the semiconductor layer and adjoining the second well region.

Abstract translation: 静电放电（ESD）保护电路包括埋氧层; 掩埋氧化物层上的半导体层; 以及第一和第二MOS器件。 第一MOS器件包括半导体层上的第一栅极; 第一阱区，具有位于第一栅极下面的部分; 以及半导体层中的第一源极区域和第一漏极区域。 第二MOS器件包括半导体层上的第二栅极; 以及具有位于第一栅极下方的部分的第二阱区。 第二阱区连接到放电节点。 第一阱区域通过第二阱区域连接到放电节点，并且不直接连接到放电节点。 第二MOS器件还包括半导体层中的第二源极区域和第二漏极区域并与第二阱区域邻接。

公开(公告)号：US07563653B2

公开(公告)日：2009-07-21

申请号：US12113803

申请日：2008-05-01

Applicant: Jian-Hsing Lee ,  Deng-Shun Chang

Inventor： Jian-Hsing Lee ,  Deng-Shun Chang

IPC: H01L21/332

CPC classification number: H01L27/0277 ,  H01L27/0255

Abstract: An electrostatic discharge (ESD) protection device includes a diode located in a substrate and an N-type metal oxide semiconductor (NMOS) device located in the substrate adjacent the diode, wherein both the diode and the NMOS are coupled to an input device, and at least a portion of the diode and at least a portion of the NMOS device collectively form an ESD protection device.

Abstract translation: 静电放电（ESD）保护装置包括位于衬底中的二极管和位于与二极管相邻的衬底中的N型金属氧化物半导体（NMOS）器件，其中二极管和NMOS都耦合到输入器件，以及 二极管的至少一部分和NMOS器件的至少一部分共同形成ESD保护器件。