公开(公告)号：US06664910B1

公开(公告)日：2003-12-16

申请号：US10460622

申请日：2003-06-13

Applicant: Jan Mulder ,  Christopher Michael Ward

Inventor： Jan Mulder ,  Christopher Michael Ward

IPC: H03M112

CPC classification number: H03K17/04106 ,  H03M1/0646 ,  H03M1/146 ,  H03M1/204 ,  H03M1/206 ,  H03M1/361 ,  H03M1/365

Abstract: An analog to digital converter includes a first amplifier array connected to taps from a reference ladder, a second amplifier array, wherein each amplifier in the first amplifier array is connected to only two amplifiers of the second amplifier array, a third amplifier array, wherein each amplifier in the second amplifier array is connected to only two amplifiers of the third amplifier array, and an encoder connected to outputs of the third amplifier array that converts the outputs to an N-bit digital signal.

公开(公告)号：US06653966B1

公开(公告)日：2003-11-25

申请号：US10359201

申请日：2003-02-06

Applicant: Franciscus Maria Leonardus van der Goes ,  Jan Mulder ,  Christopher Michael Ward ,  Jan Roelof Westra ,  Rudy van de Plassche ,  Marcel Lugthart

Inventor： Franciscus Maria Leonardus van der Goes ,  Jan Mulder ,  Christopher Michael Ward ,  Jan Roelof Westra ,  Rudy van de Plassche ,  Marcel Lugthart

IPC: H03M100

CPC classification number: H03M1/146 ,  H03K17/04106 ,  H03M1/204 ,  H03M1/365

Abstract: An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.

Abstract translation: N位模数转换器包括参考梯形图，连接到输入电压的跟踪和保持放大器，在其输入处连接到粗略电容器的粗略ADC放大器，并具有由第一时钟控制的粗略ADC复位开关 两相时钟的相位，精细ADC放大器在其输入端连接到精细电容器，并具有由两相时钟的第二时钟相位控制的精细ADC复位开关，开关矩阵从第二时钟相位选择电压子范围 参考梯形图，用于基于粗ADC放大器的输出的精细ADC放大器使用，并且其中粗电容器在第一时钟相位期间被充电到粗略的参考梯形电压，并且在第二时钟相位期间连接到T / H输出 其中精细电容器在第一时钟相位期间连接到电压子范围，并且在第二时钟相位期间连接到T / H输出;以及编码器，其将粗略和精细ADC放大器的输出转换为Nb 它输出。

公开(公告)号：US06642794B2

公开(公告)日：2003-11-04

申请号：US09920117

申请日：2001-08-01

Applicant: Jan Mulder ,  Dominicus Martinus Wilhelmus Leenaerts ,  Edwin Van Der Heijden

Inventor： Jan Mulder ,  Dominicus Martinus Wilhelmus Leenaerts ,  Edwin Van Der Heijden

IPC: H03F368

CPC classification number: H03F3/343 ,  H03F1/22 ,  H03F2200/372

Abstract: An amplifier, in particular an RF amplifier is described having an amplifier input, the amplifier comprises: a first controllable semiconductor having a first controllable mainstream path coupled to first source means for controlling the first mainstream path, and having a first biased control input; and a second controllable semiconductor having a second controllable mainstream path coupled to second source means for controlling the second mainstream path, and having a second control input coupled to the first main stream path and to the amplifier input. Both the first and second mainstream paths are coupled to a common load, and the first and second source means are arranged for controlling input impedance and noise impedance respectively of the amplifier input. This amplifier arrangement allows independent control and optimisation of both the amplifier input impedance and the noise impedance.

公开(公告)号：US06392478B1

公开(公告)日：2002-05-21

申请号：US09713864

申请日：2000-11-16

Applicant: Jan Mulder ,  Marcel Louis Lugthart

Inventor： Jan Mulder ,  Marcel Louis Lugthart

IPC: H03F136

CPC classification number: H03G1/0088 ,  G11B5/00 ,  G11B20/10009 ,  G11B2005/0016 ,  G11B2005/0018

Abstract: The invention relates to a device for amplifying electronic signals, including: an amplifier PRA, and a plurality of feedback loops G1, G2 placed between the output and the input of the amplifier, which feedback loops are arranged so that each feedback loop has an adjustable gain and all the feedback loops jointly form an assembly having an equivalent impedance which is substantially independent of the gain settings selected. Thanks to the invention, the amplification bandwidth can be easily adjusted without adversely affecting the performance of the device in terms of noise and high cut-off frequency.

Abstract translation: 本发明涉及一种用于放大电子信号的装置，包括：放大器PRA和放置在放大器的输出端和输入端之间的多个反馈回路G1，G2，该反馈回路被布置成使得每个反馈回路具有可调增益 并且所有的反馈回路共同形成具有基本上与选择的增益设置无关的等效阻抗的组件。由于本发明，可以容易地调整放大带宽，而不会对器件在噪声和高切割方面的性能产生不利影响 关闭频率