公开(公告)号：US09940097B1

公开(公告)日：2018-04-10

申请号：US14527550

申请日：2014-10-29

Applicant: Netronome Systems, Inc.

Inventor： Ronald N. Fortino ,  Gavin J. Stark ,  Steven W. Zagorianakos

IPC: G06F3/00 ,  G06F5/00 ,  G06F5/14 ,  H04L25/00 ,  G06F13/40 ,  G06F9/34 ,  H04B1/38

CPC classification number: G06F5/14 ,  G06F5/08 ,  G06F9/34 ,  G06F13/40 ,  G06F2205/126 ,  H04B1/38 ,  H04L25/00

Abstract: A registered synchronous FIFO has a tail register, internal registers, and a head register. The FIFO cannot be pushed if it is full and cannot be popped if it is empty, but otherwise can be pushed and/or popped. Within the FIFO, the internal signal fanout of incoming data circuitry and push control circuitry and is minimized and remains essentially constant regardless of the number of registers of the FIFO. The output delay of the output data also is essentially constant regardless of the number of registers of the FIFO. An incoming data value can only be written into the head or tail. If a data value is in the tail and one of the internal registers is empty, and if no push or pop is to be performed in a clock cycle, then nevertheless the data value in the tail is moved into the empty internal register in the cycle.

公开(公告)号：US09900090B1

公开(公告)日：2018-02-20

申请号：US14690362

申请日：2015-04-17

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Nicolaas J. Viljoen ,  Niel Viljoen

IPC: H04L12/24 ,  H04L12/851 ,  H04B10/079

CPC classification number: H04B10/0799 ,  H04L29/06 ,  H04L41/142 ,  H04L47/2441 ,  H04L47/2483 ,  H04L69/22 ,  H04L69/28

Abstract: An appliance receives packets that are part of a flow pair, each packet sharing an application protocol. The appliance determines the application protocol of the packets by performing deep packet inspection (DPI) on the packets. Packet sizes are measured and converted into packet size states. Packet size states, packet sequence numbers, and packet flow directions are used to create an application protocol estimation table (APET). The APET is used during normal operation to estimate the application protocol of a flow pair without performing time consuming DPI. The appliance then determines inter-packet intervals between received packets. The inter-packet intervals are converted into inter-packet interval states. The inter-packet interval states and packet sequence numbers are used to create an inter-packet interval prediction table. The appliance then stores an inter-packet interval prediction table for each application protocol. The inter-packet interval prediction table is used during operation to predict the inter-packet interval between packets.

公开(公告)号：US09891898B1

公开(公告)日：2018-02-13

申请号：US15173653

申请日：2016-06-04

Applicant: Netronome Systems, Inc.

Inventor： Johann H. Tonsing

IPC: G06F9/45 ,  G06F9/44 ,  H04L12/24 ,  H04L12/931

CPC classification number: G06F8/41 ,  G06F8/31 ,  H04L41/20 ,  H04L49/35

Abstract: A method involves compiling a first amount of high-level programming language code (for example, P4) and a second amount of a low-level programming language code (for example, C) thereby obtaining a first section of native code and a second section of native code. The high-level programming language code at least in part defines how an SDN switch performs matching in a first condition. The low-level programming language code at least in part defines how the SDN switch performs matching in a second condition. The low-level code can be a type of plugin or patch for handling special packets. The sections of native code are loaded into the SDN switch such that a first processor (for example, x86 of the host) executes the first section of native code and such that a second processor (for example, ME of an NFP on the NIC) executes the second section of native code.

公开(公告)号：US09866480B1

公开(公告)日：2018-01-09

申请号：US14927455

申请日：2015-10-29

Applicant: Netronome Systems Inc.

Inventor： Hetal S. Borad ,  Gavin J. Stark ,  Ron L. Swartzentruber

IPC: H04L12/743 ,  G06F3/06

CPC classification number: H04L45/7453 ,  G06F3/0613 ,  G06F3/0659 ,  G06F3/067

Abstract: A novel hash range lookup command is disclosed. In an exemplary embodiment, a method includes (a) providing access to a hash table that includes hash buckets having hash entry fields; (b) receiving a novel hash lookup command; (c) using the hash lookup command to determine hash command parameters, a hashed index value, and a flow key value; (d) using the hash command parameters and the hashed index value to generate hash values (addresses) to access entry fields in a selectable number of hash buckets; (e) comparing bits of the entry value in the entry field to bits of the flow key value; (f) repeating (d) through (e) until a match is determined or until the selectable number of hash buckets and entries have been accessed; and (g) returning either an address of the entry field containing the match or a result associated with the entry field containing the match.

公开(公告)号：US09804959B2

公开(公告)日：2017-10-31

申请号：US14530599

申请日：2014-10-31

Applicant: Netronome Systems, Inc.

Inventor： Salma Mirza ,  Steven W. Zagorianakos ,  Gavin J. Stark

IPC: G06F9/46 ,  G06F15/173 ,  G06F12/02 ,  H04L29/06

CPC classification number: G06F12/023 ,  G06F12/0223 ,  G06F2212/174 ,  G06F2212/254 ,  H04L69/22

Abstract: A method for supporting in-flight packet processing is provided. Packet processing devices (microengines) can send a request for packet processing to a packet engine before a packet comes in. The request offers a twofold benefit. First, the microengines add themselves to a work queue to request for processing. Once the packet becomes available, the header portion is automatically provided to the corresponding microengine for packet processing. Only one bus transaction is involved in order for the microengines to start packet processing. Second, the microengines can process packets before the entire packet is written into the memory. This is especially useful for large sized packets because the packets do not have to be written into the memory completely when processed by the microengines.

公开(公告)号：US09756152B1

公开(公告)日：2017-09-05

申请号：US14726423

申请日：2015-05-29

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Stuart C. Wray

IPC: H04L29/06 ,  H04L12/741

CPC classification number: H04L69/22 ,  H04L45/745 ,  H04L47/2441

Abstract: An exact-match flow table structure stores flow entries. Each flow entry includes a Flow Id and an action value. A flow entry is generated from an incoming packet. The flow table structure determines whether there is a stored flow entry, the Flow Id of which is an exact-match for generated Flow Id. In one novel aspect, a multiplexer circuit is used to generate Flow Ids. The multiplexer circuit includes a plurality of byte-wide multiplexer. Each respective one of the byte-wide multiplexers outputs a byte that is a corresponding respective byte of the Flow Id. The various inputs of the byte-wide multiplexers are coupled to receive various bytes of the incoming packet, various bytes of modified or compressed packet data, as well as bytes of metadata. By controlling select values supplied onto the select inputs of the multiplexer circuit, Flow Ids of different forms can be generated.

公开(公告)号：US09755911B1

公开(公告)日：2017-09-05

申请号：US14923458

申请日：2015-10-27

Applicant: Netronome Systems, Inc.

Inventor： Johann H. Tönsing

IPC: H04L12/28 ,  H04L12/24 ,  H04L12/751 ,  H04L12/935

CPC classification number: H04L41/12 ,  H04L43/0876 ,  H04L45/02 ,  H04L45/24 ,  H04L45/38 ,  H04L49/3009

Abstract: A networking device includes a match table maintained on a first processor. The match table includes an entry that in turn includes an entry packet count. Packets of multiple flows result in matches to the entry. A set of bypass packet counts is maintained on a second processor of the networking device. There is one bypass packet count for each of the multiple paths through the first processor. A request for a “system entry packet count” of an entry located in a match table on the first processor is received onto the networking device. All paths of all flows that could have resulted in matches of that entry are determined. The “system entry packet count” is then determined by summing the entry packet count and the bypass packet counts for all those paths. A response is output from the networking device, where the response includes the “system entry packet count”.

公开(公告)号：US09727673B1

公开(公告)日：2017-08-08

申请号：US14885978

申请日：2015-10-16

Applicant: Netronome Systems, Inc.

Inventor： Jason Scott McMullan ,  David Alton Welch

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G06F17/5022 ,  G06F17/5081 ,  G06F2217/04

Abstract: An integrated circuit includes a first circuit, a second circuit, and a bus that couples the circuits together. The first circuit is simulated on a first simulator at the same time that the second circuit is simulated on a second simulator. A simulator plug-in is incorporated into the simulation model of the first circuit. A simulator plug-in is incorporated into the simulation model of the second circuit. If valid data is to pass from the first to second circuit across the bus during simulation, then the plug-in of the first model causes a network stack to generate a packet. The packet carries the data. After communication to the second simulator, the data is recovered from the packet, and is injected by the plug-in of the second model into the simulation of the second circuit. By exchanging data back and forth this way, multiple circuits are simulated simultaneously on different simulators.

公开(公告)号：US09727513B1

公开(公告)日：2017-08-08

申请号：US14530760

申请日：2014-11-02

Applicant: Netronome Systems, Inc.

Inventor： Ron Lamar Swartzentruber

IPC: G06F13/36 ,  G06F13/40 ,  G06F3/06

CPC classification number: G06F13/4027 ,  G06F3/0613 ,  G06F3/0647 ,  G06F3/0683

Abstract: A method of performing an unicast packet ready command (unicast mode operation) is described herein. A packet ready command is received from a memory system via a bus and onto a network interface circuit. The packet ready command includes a multicast value. A communication mode is determined as a function of the multicast value. The multicast value indicates a single packet is to be communicated to a single destination by the network interface circuit. A free packet command is outputted from the network interface circuit onto the bus. The free packet command includes a Free On Last Transfer (FOLT) value that indicates that the packet is to be freed from the memory system by the network interface circuit after the packet is communicated to the network interface circuit. The network interface circuit and the memory system are included on an Island-Based Network Flow Processor.

公开(公告)号：US09727499B2

公开(公告)日：2017-08-08

申请号：US14074469

申请日：2013-11-07

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F13/16 ,  G06F13/362 ,  G06F13/364

CPC classification number: G06F13/1663 ,  G06F13/3625 ,  G06F13/364

Abstract: A First Come First Server (FCFS) arbiter that receives a request to utilize a shared resource from a plurality of devices and in response generates a grant value indicating if the request is granted. The FCFS arbiter includes a circuit and a storage device. The circuit receives a first request and a grant enable during a first clock cycle and outputs a grant value. The grant enable is received from a shared resource. The grant value communicated to the source of the first request. The storage device includes a plurality of request buckets. The first request is stored in a first request bucket when the first request is not granted during the first clock cycle and is moved from the first request bucket to a second request bucket when the first request is not granted during a second clock cycle. A granted request is cleared from all request buckets.