公开(公告)号：US20250014872A1

公开(公告)日：2025-01-09

申请号：US18887050

申请日：2024-09-17

Applicant: Tokyo Electron Limited

Inventor： Chishio KOSHIMIZU

IPC: H01J37/32

Abstract: A plasma processing method includes (a) generating plasma in a chamber of a plasma processing apparatus including a substrate support provided in the chamber and supporting a substrate placed thereon, (b) applying a voltage pulse from a bias power supply to a bias electrode of the substrate support in order to draw ions from the plasma into the substrate, and (c) repeating (b). In (c), a duration length of the voltage pulse is changed to change a potential of the substrate.

公开(公告)号：US20250014864A1

公开(公告)日：2025-01-09

申请号：US18755946

申请日：2024-06-27

Applicant: Tokyo Electron Limited

Inventor： Masaki HIRAYAMA

IPC: H01J37/32

Abstract: A plasma processing apparatus includes a chamber, a substrate support, an excitation electrode, and a resonator. The resonator includes an inner side portion and an outer side portion extending coaxially, and conductive plates arranged parallel to each other in a vertical direction. The resonator provides a waveguide path extending between the inner and outer side portions and including a plurality of layers arranged alternately with the conductive plates. Each of the plurality of layers is connected to a layer thereabove at one of a plurality of folded portions along the inner side portion or the outer side portion. A lowermost conductive plate includes a plurality of slots electromagnetically coupled to the discharger. The plurality of slots is arranged in a circumferential direction, and a wall surrounding a lowermost layer in the outer side portion extends along sides of a polygon.

公开(公告)号：US12191297B2

公开(公告)日：2025-01-07

申请号：US17867833

申请日：2022-07-19

Applicant: Tokyo Electron Limited

Inventor： Robert Clark

IPC: H01L21/78 ,  G03F1/42 ,  G06F30/31 ,  H01L23/528 ,  H01L25/00 ,  H01L25/065

Abstract: In certain embodiments, a method for designing a semiconductor device includes generating a 2D design for fabricating chiplets on a substrate. The chiplets are component levels for a multi-chip integrated circuit. The 2D design includes a first layout for alignment features and semiconductor structures to be formed on a first surface of a first chiplet and a second layout for alignment features and semiconductor structures to be formed on a first surface of a second chiplet. The first and second chiplets are adjacent on the substrate. The second layout is a mirror image of the first layout across a reference line shared by the first and second chiplets. The first surfaces of the first and second chiplets are both either top or bottom surfaces. The method further includes generating one or more photomasks according to the design.

公开(公告)号：US12191149B2

公开(公告)日：2025-01-07

申请号：US17772163

申请日：2020-09-11

Applicant: Tokyo Electron Limited

Inventor： Hayato Tanoue ,  Yohei Yamashita

IPC: B23K26/53 ,  B24B7/22 ,  H01L21/268 ,  H01L21/304 ,  B23K103/00

Abstract: A substrate processing method of processing a combined substrate in which a first substrate and a second substrate are bonded to each other includes forming a peripheral modification layer along a boundary between a peripheral portion of the first substrate as a removing target and a central portion of the first substrate; forming a non-bonding region in which bonding strength between the first substrate and the second substrate in the peripheral portion is reduced; and removing the peripheral portion starting from the peripheral modification layer. A first crack is developed from the peripheral modification layer toward the second substrate. The peripheral modification layer is formed such that a lower end of the first crack is located above the non-bonding region and an inner end of the non-bonding region is located at a diametrically outer side than the first crack.

公开(公告)号：US12188125B2

公开(公告)日：2025-01-07

申请号：US17805062

申请日：2022-06-02

Applicant: Tokyo Electron Limited

Inventor： Takanobu Hotta ,  Takuya Kawaguchi ,  Hideaki Yamasaki ,  Toshio Takagi ,  Takashi Kakegawa

IPC: C23C16/455 ,  C23C16/44

Abstract: A showerhead includes a shower plate, a base member in which a gas flow passage is provided, the base member fixing the shower plate, a plurality of gas supply members disposed in a gas diffusion space and connected to the gas flow passage, the gas diffusion space being formed between the shower plate and the base member, and a flow adjusting plate disposed in the gas diffusion space, the flow adjusting plate being disposed on an outer periphery on an outer side from the plurality of gas supply members.

公开(公告)号：US20250006541A1

公开(公告)日：2025-01-02

申请号：US18754701

申请日：2024-06-26

Applicant: Tokyo Electron Limited

Inventor： Riichiro ENDO ,  Takehiro TANIKAWA ,  Kazuma KITA

IPC: H01L21/683 ,  H01J37/32 ,  H01L21/67

Abstract: A substrate-processing apparatus includes a substrate support that includes an electrostatic chuck, the electrostatic chuck including a support surface configured to support an annular member. The support surface includes a diffusion groove through which a heat transfer gas is diffused into a gap between the annular member and the support surface. The diffusion groove includes an annular groove provided concentrically with the electrostatic chuck; and a radial groove that is in communication with the annular groove and is provided from the annular groove in a radial direction of the electrostatic chuck.

公开(公告)号：US20250003874A1

公开(公告)日：2025-01-02

申请号：US18698613

申请日：2022-09-26

Applicant: Tokyo Electron Limited

Inventor： Yuji OTSUKI

IPC: G01N21/552 ,  C23C16/52 ,  G01N21/3563 ,  G01N21/84 ,  H01L21/66

Abstract: A measurement method includes: a first measurement step of irradiating a prism with infrared light and measuring reflected light totally reflected by the prism; a second measurement step of irradiating the prism with infrared light while the prism is arranged on a substrate and measuring reflected light totally reflected by a surface of the prism on the substrate; and a calculation step of calculating an absorbance spectrum from an intensity spectrum of infrared light for each wave number of the reflected light measured in the first measurement step and an intensity spectrum of infrared light for each wave number of the reflected light measured in the second measurement step.

公开(公告)号：US20240429031A1

公开(公告)日：2024-12-26

申请号：US18824128

申请日：2024-09-04

Applicant: Tokyo Electron Limited ,  Nagoya Institute of Technology

Inventor： Masanori SATO ,  Atsushi KAWABATA ,  Ryusei KASHIMURA ,  Jun HIROSE ,  Kunihiko KATO ,  Takashi SHIRAI

IPC: H01J37/32 ,  H01J9/00

Abstract: An alumina ceramic member contains an alumina polycrystal with an average grain size less than or equal to 100 μm. The alumina ceramic member is doped with yttrium in a state other than a crystalline state of an oxide, a crystalline state of a garnet structure, or an amorphous state, at grain boundaries of the alumina polycrystal.

公开(公告)号：US20240429027A1

公开(公告)日：2024-12-26

申请号：US18830771

申请日：2024-09-11

Applicant: Tokyo Electron Limited

Inventor： Noriyuki SAKAYA ,  Sho SAITOH ,  Yoshimitsu KON

IPC: H01J37/32

Abstract: A plasma processing apparatus includes a plasma processing chamber; a substrate support disposed within the plasma processing chamber and including a lower electrode; an upper electrode disposed above the substrate support; and an RF power supply configured to supply an RF signal to the upper electrode or the lower electrode, the RF signal having a first power level during a first sub-period in a repetition period and a second power level during a second sub-period in the repetition period; and a DC power supply configured to supply a DC signal to the lower electrode. The DC signal has an OFF-state during a delay period in the first sub-period, has a sequence of a plurality of DC pulses during the first sub-period excluding the delay period, and has an OFF-state during the second sub-period, the delay period being within a range of 2% to 7% of the repetition period.

公开(公告)号：US20240427317A1

公开(公告)日：2024-12-26

申请号：US18747506

申请日：2024-06-19

Applicant: Tokyo Electron Limited

Inventor： Ryota AOI ,  Kenichi KOBAYASHI

IPC: G05B19/418 ,  H01L21/67

Abstract: A control device for controlling a semiconductor manufacturing apparatus including a local operation terminal displaying an apparatus screen of the semiconductor manufacturing apparatus and one or more remote operation terminals displaying the apparatus screen, includes: a login state management unit that manages the local operation terminal and at least one of the remote operation terminals that are logged into the same semiconductor manufacturing apparatus; and a communication unit that provides a function of posting and browsing a message between a first user operating the local operation terminal and a second user operating the at least one of the remote operation terminals that are logged into the same semiconductor manufacturing apparatus, by transmitting screen data enabling the posting and browsing of the message to the local operation terminal and the at least one of the remote operation terminals that are logged into the same semiconductor manufacturing apparatus.