公开(公告)号：US07138831B2

公开(公告)日：2006-11-21

申请号：US10978782

申请日：2004-11-02

申请人： Youichi Tobita

发明人： Youichi Tobita

IPC分类号： H03K19/0175

CPC分类号： G09G3/20 ,  G09G2310/027 ,  G09G2310/0289 ,  G09G2310/0294 ,  H03K19/01855 ,  H03M9/00

摘要： A MOS capacitor receiving a clock signal complementary to a sampling clock signal is provided at an input of a clocked inverter that is activated after sampling an input signal to perform level conversion. A charge pump operation of the MOS capacitor is performed in parallel with the activation of the clocked inverter. The power consumption of and the area occupied by a level conversion circuit converting a voltage amplitude of the input signal are reduced without deteriorating a high-speed operating characteristics.

摘要翻译： 接收时钟信号与采样时钟信号互补的MOS电容器被提供在时钟反相器的输入端，该时钟反相器在对输入信号采样之后被激活以执行电平转换。 与时钟反相器的激活并行地执行MOS电容器的电荷泵操作。 转换输入信号的电压振幅的电平转换电路所占用的功耗和面积减小，而不会降低高速工作特性。

公开(公告)号：US07034571B2

公开(公告)日：2006-04-25

申请号：US10836266

申请日：2004-05-03

申请人： Youichi Tobita

发明人： Youichi Tobita

IPC分类号： H03K19/0175 ,  H03K19/094

CPC分类号： H03K17/223 ,  H03K19/01714 ,  H03K19/018507

摘要： A gate of an N-channel MOS transistor driving an output node is driven through a capacitance element in accordance with an input signal. A voltage on a source node of the drive transistor is applied as an output signal to an output node. Consequently, it is possible to perform level conversion of a voltage at a low level of the input signal having a higher voltage than the source node voltage of the drive transistor. It is thus possible to achieve a level converting circuit that can reduce the number of manufacturing steps, and can perform the level conversion of any logical level of the input signal.

摘要翻译： 驱动输出节点的N沟道MOS晶体管的栅极根据输入信号被驱动通过电容元件。 将驱动晶体管的源极节点上的电压作为输出信号施加到输出节点。 因此，可以进行具有比驱动晶体管的源节点电压高的电压的输入信号的低电平的电压的电平转换。 因此，可以实现能够减少制造步骤数量的电平转换电路，并且可以执行输入信号的任何逻辑电平的电平转换。

公开(公告)号：US20060007215A1

公开(公告)日：2006-01-12

申请号：US11147370

申请日：2005-06-08

申请人： Youichi Tobita ,  Masafumi Agari

发明人： Youichi Tobita ,  Masafumi Agari

IPC分类号： G09G5/00

CPC分类号： G09G3/3241 ,  G09G3/3266 ,  G09G3/3283 ,  G09G3/3291 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2310/0248 ,  G09G2310/0251

摘要： A plurality of data lines are provided for pixels arranged in one column. One of the data lines is precharged to a predetermined voltage, and a write current of a voltage corresponding to black data is supplied to a selected pixel via another data line. These data lines are connected to the pixels in different rows in a predetermined sequence. A display device capable of writing a complete black signal without impairing a margin for a write time can be provided.

摘要翻译： 为一列设置的像素提供多条数据线。 其中一条数据线被预充电到预定的电压，并且与黑色数据相对应的电压的写入电流通过另一数据线提供给所选择的像素。 这些数据线以预定的顺序连接到不同行中的像素。 可以提供能够写入完整的黑色信号而不损害写入时间的余量的显示装置。

公开(公告)号：US20050275607A1

公开(公告)日：2005-12-15

申请号：US11128308

申请日：2005-05-13

申请人： Youichi Tobita

发明人： Youichi Tobita

IPC分类号： H01L51/50 ,  G09G3/20 ,  G09G3/30 ,  G09G3/32 ,  H05B33/14

CPC分类号： G09G3/3283 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2300/0861 ,  G09G2300/0866 ,  G09G2310/0256 ,  G09G2320/043

摘要： A pixel drive circuit includes a drain voltage increase limiter circuit composed of a TFT device provided between a node and the drain of a TFT device serving as a current source, a capacitor and a switch. In a data write mode, switches are turned on to allow drive curent to flow from a data line to the TFT devices. Then, respective gate voltages of the TFT devices are held in respective capacitors. In a display mode, only a switch is turned on to form a current path from a supply voltage to the TFT devices through a light-emitting diode. The voltage on a node is held constant regardless of channel modulation. Accordingly, desired electric current flows through the light-emitting diode.

摘要翻译： 像素驱动电路包括由设置在用作电流源的TFT器件的节点和漏极之间的TFT器件，电容器和开关构成的漏极电压增加限制电路。 在数据写入模式下，开关导通，使驱动器从数据线流向TFT器件。 然后，将TFT器件的各个栅极电压保持在各自的电容器中。 在显示模式中，只有开关导通，以通过发光二极管形成从电源电压到TFT器件的电流路径。 无论通道调制如何，节点上的电压都保持不变。 因此，期望的电流流过发光二极管。

公开(公告)号：US06388934B1

公开(公告)日：2002-05-14

申请号：US09832958

申请日：2001-04-12

申请人： Youichi Tobita

发明人： Youichi Tobita

IPC分类号： G11C700

CPC分类号： G11C11/406 ,  G11C11/404 ,  G11C11/40603 ,  G11C11/4096 ,  H01L21/02074 ,  H01L21/31055 ,  H01L21/31058 ,  H01L21/3212 ,  H01L21/76819 ,  H01L21/7684

摘要： Column select gates are provided to normal bit lines and refresh bit lines, respectively. When a refresh request and a data access instruction are applied on the same row, it is determined which of refresh and data access is instructed earlier, and one of a normal bit line pair and a refresh bit line pair is connected to an internal data line pair according to the determination result. A semiconductor memory device is provided by which access time is not increased even when refresh and ordinary access conflict with each other.

摘要翻译： 列选择栅极分别提供给普通位线和刷新位线。 当在同一行上应用刷新请求和数据访问指令时，确定更早地指示刷新和数据访问中的哪一个，并且正常位线对和刷新位线对中的一个连接到内部数据线 根据确定结果进行配对。 提供一种半导体存储器件，即使在刷新和普通访问彼此冲突时，访问时间也不会增加。

公开(公告)号：US06222223B1

公开(公告)日：2001-04-24

申请号：US09395987

申请日：1999-09-15

申请人： Youichi Tobita

发明人： Youichi Tobita

IPC分类号： H01L27108

CPC分类号： H01L28/82 ,  H01L27/108

摘要： First conductive layers having structures similar to that of a storage node of a memory cell capacitor are isolated from each other, and are commonly and electrically connected to a third conductive layer. A second conductive layer corresponding to a cell plate of the memory cell capacitor is formed on the first conductive layers with a capacitor insulating film therebetween. Opposed portions of the first and second conductive layers have large areas, so that a large number of parallel unit capacitance elements can be formed within a limited area, and a capacitance element can have a good area efficiency.

摘要翻译： 具有与存储单元电容器的存储节点类似的结构的第一导电层彼此隔离，并且通常并电连接到第三导电层。 对应于存储单元电容器的单元板的第二导电层在其间具有电容器绝缘膜的第一导电层上形成。 第一导电层和第二导电层的相对部分具有大的面积，从而可以在有限的区域内形成大量的并联单元电容元件，并且电容元件可以具有良好的面积效率。

公开(公告)号：US5986915A

公开(公告)日：1999-11-16

申请号：US154734

申请日：1998-09-17

申请人： Hiromi Okimoto ,  Masanori Hayashikoshi ,  Youichi Tobita

发明人： Hiromi Okimoto ,  Masanori Hayashikoshi ,  Youichi Tobita

IPC分类号： G06F11/20 ,  G11C8/08 ,  G11C8/10 ,  G11C29/00 ,  G11C7/00

CPC分类号： G06F11/2007 ,  G11C29/70 ,  G11C29/78 ,  G11C29/832 ,  G11C8/08 ,  G11C8/10

摘要： A column select line includes a first layer column select line and a second layer column select line formed above the first layer column select line and connected thereto at any point. Furthermore, clamping circuits each for clamping each word line of paired main word lines at a constant potential are provided in a semiconductor memory device having main and secondary word line structure. With such a structure, malfunction due to multiselection of memory cells can be avoided even when the column select line or the paired main word lines is disconnected.

摘要翻译： 列选择线包括形成在第一层列选择线上方并在任何点连接的第一层列选择线和第二层列选择线。 此外，在具有主字线和次级字线结构的半导体存储器件中提供各自用于将一对主字线的每个字线固定为恒定电位的钳位电路。 利用这种结构，即使当列选择线或成对的主字线断开时，也可以避免由于存储器单元的多选而导致的故障。

公开(公告)号：US5523977A

公开(公告)日：1996-06-04

申请号：US62493

申请日：1993-05-18

申请人： Youichi Tobita ,  Yasuji Nagayama

发明人： Youichi Tobita ,  Yasuji Nagayama

IPC分类号： G11C11/404 ,  G11C11/401 ,  G11C29/00 ,  G11C29/46 ,  G11C29/50 ,  G11C7/00

CPC分类号： G11C29/50012 ,  G11C29/46 ,  G11C29/50 ,  G11C11/401 ,  G11C2029/5004

摘要： A semiconductor memory device having a test circuit includes voltage detection circuits (120, 220) for detecting a test mode when a voltage higher than a normal use voltage is applied to a terminal (101, 201). When one voltage detection circuit (120) detects a test mode, a voltage switching circuit (130) renders a MOS transistor (111) conductive, a resistance (115) connected in parallel to the MOS transistor is short-circuited and a voltage lower than (1/2.multidot.Vcc) is applied to a bit line voltage supply line (9). Alternatively, when the other voltage detection circuit (220) detects the test mode, a voltage switching circuit (230) renders a MOS transistor (211) conductive, a resistance (114) connected in parallel to the MOS transistor is short-circuited, and a voltage higher than (1/2.multidot.Vcc) is applied to the bit line voltage supply line. Thus, by applying a voltage higher or lower than that for normal use on a bit line, a memory cell having a small margin can be tested in a short period of time.

摘要翻译： 具有测试电路的半导体存储器件包括当对端子（101,201）施加高于正常使用电压的电压时，用于检测测试模式的电压检测电路（120,220）。 当一个电压检测电路（120）检测到测试模式时，电压切换电路（130）使MOS晶体管（111）导通，与MOS晶体管并联连接的电阻（115）短路，电压低于 （1 / 2xVcc）施加到位线电压供给线（9）。 或者，当另一个电压检测电路（220）检测到测试模式时，电压切换电路（230）使MOS晶体管（211）导通，与MOS晶体管并联连接的电阻（114）短路， 将高于（1 / 2xVcc）的电压施加到位线电压供应线。 因此，通过在位线上施加比正常使用的电压更高或更低的电压，可以在短时间内测试具有小余量的存储单元。

公开(公告)号：US5418747A

公开(公告)日：1995-05-23

申请号：US220649

申请日：1994-03-31

申请人： Youichi Tobita

发明人： Youichi Tobita

IPC分类号： G11C11/409 ,  G11C11/407 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4091 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C11/4074 ,  G11C11/4076 ,  G11C11/4091

摘要： A dynamic random access memory having a plurality of rated voltages as an operation supply voltage operates accurately with a sufficient operating margin for each rated voltage. The dynamic random access memory has a circuit for generating a signal for defining operation speed/timing of a sense amplifier depending on the operation supply voltage, and a circuit for driving the sense amplifier in response to an output of a defining signal generating circuit. The sense amplifier driving circuit comprises a first gate for transmitting a sense amplifier activating signal as it is in response to the defining signal, a second gate for passing therethrough a sense amplifier activating signal passed through a delay circuit in response to the defining signal, and transistors for driving the sense amplifier in response to outputs of the first and second gates. One of the first and second gates is activated by the defining signal. An operation speed/timing instructing signal is applied externally or from a supply voltage detecting circuit. In the case that rated values are varied depending on an operation mode, there are provided a circuit for detecting the operation mode in response to activating timings of a row address strobe signal, a column address strobe signal and a write signal, and a circuit for generating a defining signal in response to an output of this operation mode detecting circuit and the operation speed/timing instructing signal.

摘要翻译： 具有作为操作电源电压的多个额定电压的动态随机存取存储器以每个额定电压具有足够的工作裕度来精确地操作。 动态随机存取存储器具有用于根据操作电源电压产生用于定义读出放大器的操作速度/定时的信号的电路，以及响应于定义信号发生电路的输出来驱动读出放大器的电路。 读出放大器驱动电路包括用于响应于定义信号传输读出放大器激活信号的第一门，用于响应于定义信号通过延迟电路的读出放大器激活信号的第二门，以及 用于响应于第一和第二栅极的输出驱动读出放大器的晶体管。 第一和第二门之一由定义信号激活。 在外部或从电源电压检测电路施加操作速度/定时指示信号。 在额定值根据操作模式而变化的情况下，提供了用于响应于行地址选通信号，列地址选通信号和写信号的激活定时检测操作模式的电路，以及用于 响应于该操作模式检测电路的输出和操作速度/定时指示信号产生定义信号。

公开(公告)号：US5267200A

公开(公告)日：1993-11-30

申请号：US399946

申请日：1989-08-31

申请人： Youichi Tobita

发明人： Youichi Tobita

IPC分类号： G11C7/10 ,  G11C11/00

CPC分类号： G11C7/1033

摘要： A semiconductor memory device comprises a memory cell array (1) comprising a plurality of memory cells (MC) arranged in a matrix. A Y decoder (5) is responsive to an external address signal for outputting a selecting signal which simultaneously selects a plurality of columns in the memory cell array (1). The selecting signal is held by a latch transistor (LT). A selector (9b) sequentially applies input data to a plurality of columns simultaneously selected by the selecting signal held by the latch transistor (LT). During operation of the selector (9b), a binary counter (11) generates the subsequent internal column address signal, to which the Y decoder (5) is responsive for generating a selecting signal which simultaneously selects another plurality of columns in the memory cell array (1). As a result, the selecting operation in response to the subsequent selecting signal is performed immediately after operation of the selector (9b) is accomplished.

摘要翻译： 半导体存储器件包括存储单元阵列（1），其包括以矩阵形式布置的多个存储单元（MC）。 Y解码器（5）响应外部地址信号，输出同时选择存储单元阵列（1）中的多个列的选择信号。 选择信号由锁存晶体管（LT）保持。 选择器（9b）顺序地将输入数据施加到由锁存晶体管（LT）保持的选择信号同时选择的多个列。 在选择器（9b）的操作期间，二进制计数器（11）产生随后的内部列地址信号，Y解码器（5）响应于其产生同时选择存储单元阵列中的另外多个列的选择信号 （1）。 结果，在完成了选择器（9b）的操作之后立即执行响应于随后的选择信号的选择操作。