OLED display panel and display device

    公开(公告)号:US10510814B2

    公开(公告)日:2019-12-17

    申请号:US15744499

    申请日:2017-06-13

    Abstract: An OLED display panel and a display device are provided. An image sensor is added below OLED light-emitting devices, a light shielding layer including at least one pinhole imaging region is added between the image sensor and the OLED light emitting device, with the pinhole imaging region corresponding to a gap position between the OLED light-emitting devices in the light shielding layer and staggered from light shielding parts in a signal routing and a control device, an object located above the OLED display panel is imaged on the image sensor.

    DISPLAY PANEL AND MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE INCLUDING DISPLAY PANEL

    公开(公告)号:US20190173054A1

    公开(公告)日:2019-06-06

    申请号:US16107676

    申请日:2018-08-21

    Inventor: Libin Liu Zheng Liu

    Abstract: The present disclosure discloses a display panel, which includes a thin-film transistor arranged on a substrate, an electroluminescent diode arranged on the thin-film transistor, which includes a bottom electrode, a light emitting layer, and a top electrode, and a thin-film encapsulation layer covering the electroluminescent diode. The display panel further includes an auxiliary electrode and a lead wire of the top electrode of the electroluminescent diode. The auxiliary electrode is electrically connected to the lead wire of the top electrode of the electroluminescent diode by penetrating through a via hole of the thin-film encapsulation layer. Arrangements of the present disclosure provide a display panel and a manufacturing method thereof and a display device including the display panel.

    Array substrate, and display device, and fabrication methods

    公开(公告)号:US10249763B2

    公开(公告)日:2019-04-02

    申请号:US15528215

    申请日:2016-12-12

    Abstract: A semiconductor device, an array substrate, and a display device, and their fabrication methods are provided. An exemplary semiconductor device includes a first electrode, an insulating layer, and a second electrode, over a substrate. A conductive layer is on the insulating layer. A semiconductor layer is on the first electrode, on a first sidewall of the insulating layer, on the conductive layer, on the second sidewall of the insulating layer, and on the second electrode. A first gate electrode is over a portion of the semiconductor layer that is on the first sidewall of the insulating layer. A second gate electrode is over a portion of the semiconductor layer that is on the second sidewall of the insulating layer.

    SHIFT REGISTER UNIT AND DRIVING METHOD, GATE DRIVE CIRCUIT, AND DISPLAY APPARATUS

    公开(公告)号:US20180144677A1

    公开(公告)日:2018-05-24

    申请号:US15508608

    申请日:2016-09-22

    Abstract: The present application discloses a shift register unit for outputting a gate driving signal to control image display in an operation cycle including sequentially an input phase, an output phase, an output-suspending phase, the shift register unit including a first node-control circuit connected to a pull-up node and a first pull-down node; a second node-control circuit connected to a pull-down control node and the pull-up node; a pull-up circuit connected to the pull-up node, a first input terminal for receiving a first clock signal, and an output terminal for outputting the gate driving signal, and configured to control the first clock signal to be passed from the first input terminal to the output terminal when the pull-up node is at a first potential level; a third node-control circuit connected to the pull-up node, the first pull-down node, the pull-down control node, and a second input terminal for receiving a second clock signal; and configured to control the first pull-down node to receive the second clock signal from the second input terminal when the pull-down control node is at the first potential level; a first pull-down circuit connected to the first pull-down node and the output terminal to control a second potential level to be passed to the output terminal when the first pull-down node is at the first potential level; a fourth node-control circuit connected to a second pull-down node and the pull-down control node to control the second pull-down node at the second potential level during the input phase and the output phase and to maintain an inverted potential level between the second pull-down node and the first pull-down node during the output-suspending phase; and a second pull-down circuit connected to the second pull-down node and the output terminal to yield a second potential level at the output terminal when the second pull-down node is at the first potential level, the first node-control circuit being further connected to the second pull-down node to control the pull-up node at the second potential level when the second pull-down node is at the first potential level.

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