公开(公告)号：US5686354A

公开(公告)日：1997-11-11

申请号：US478324

申请日：1995-06-07

申请人： Steven Avanzino ,  Subhash Gupta ,  Rich Klein ,  Scott D. Luning ,  Ming-Ren Lin

发明人： Steven Avanzino ,  Subhash Gupta ,  Rich Klein ,  Scott D. Luning ,  Ming-Ren Lin

IPC分类号： H01L21/768 ,  H01L21/28

CPC分类号： H01L21/76831 ,  H01L21/76807

摘要： A dual damascene method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using a thin protective via mask to form the via openings. A conductive line mask pattern is used to form conductive line openings in an insulating layer. Next, a thin protective layer of conformal material is deposited in the conducive line opening. The protective layer and the insulating layer each have etch resistance to others etchant. Using a via mask pattern, openings are etching the protective layer with the insulating layer serving as and etch stop. Next via openings are etched in the insulating material using the openings in the thin protective layer as the etch mask. If the protective layer is a conductive material, it is removed from the surface of the insulating layer either before or after the conductive line and via openings are filled with a conductive material. If the protective material is an insulating material, it is entirely removed before filling the conductive line and via openings conductive material.

摘要翻译： 一种双镶嵌方法，用于制造导线的互连级别并且连接用于集成电路的绝缘和用于半导体器件的衬底载体的通孔，其使用薄的保护性通孔掩模形成通孔。 导电线掩模图案用于在绝缘层中形成导电线路开口。 接下来，在导电线路开口中沉积有保形材料的薄保护层。 保护层和绝缘层各自具有对其它蚀刻剂的耐蚀刻性。 使用通孔掩模图案，开口蚀刻保护层，绝缘层用作蚀刻停止。 接下来通过开口被蚀刻在绝缘材料中，使用薄保护层中的开口作为蚀刻掩模。 如果保护层是导电材料，则在导电线之前或之后将其从绝缘层的表面去除，并且通孔开口填充有导电材料。 如果保护材料是绝缘材料，则在填充导电线和通孔开口导电材料之前将其完全去除。

公开(公告)号：US07871873B2

公开(公告)日：2011-01-18

申请号：US12413174

申请日：2009-03-27

申请人： Witold Maszara ,  Ming-Ren Lin ,  Jin Cho ,  Zoran Krivokapic

发明人： Witold Maszara ,  Ming-Ren Lin ,  Jin Cho ,  Zoran Krivokapic

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/336

CPC分类号： H01L29/66795

摘要： A method of manufacturing semiconductor fins for a semiconductor device may begin by providing a bulk semiconductor substrate. The method continues by growing a layer of first epitaxial semiconductor material on the bulk semiconductor substrate, and by growing a layer of second epitaxial semiconductor material on the layer of first epitaxial semiconductor material. The method then creates a fin pattern mask on the layer of second epitaxial semiconductor material. The fin pattern mask has features corresponding to a plurality of fins. Next, the method anisotropically etches the layer of second epitaxial semiconductor material, using the fin pattern mask as an etch mask, and using the layer of first epitaxial semiconductor material as an etch stop layer. This etching step results in a plurality of fins formed from the layer of second epitaxial semiconductor material.

摘要翻译： 制造用于半导体器件的半导体鳍片的方法可以通过提供体半导体衬底开始。 该方法通过在体半导体衬底上生长第一外延半导体材料层并通过在第一外延半导体材料层上生长第二外延半导体材料层来继续。 该方法然后在第二外延半导体材料层上产生鳍状图案掩模。 翅片图形掩模具有对应于多个翅片的特征。 接下来，使用鳍图案掩模作为蚀刻掩模，并且使用第一外延半导体材料层作为蚀刻停止层，该方法各向异性地蚀刻第二外延半导体材料的层。 该蚀刻步骤导致由第二外延半导体材料层形成的多个鳍片。

公开(公告)号：US07713834B2

公开(公告)日：2010-05-11

申请号：US12205361

申请日：2008-09-05

申请人： Haihong Wang ,  Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

发明人： Haihong Wang ,  Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

IPC分类号： H01L21/76

CPC分类号： H01L21/76224 ,  H01L21/823481 ,  H01L29/1054

摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a ALD process.

摘要翻译： 集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。 浅沟槽隔离技术用于应变硅（SMOS）工艺。 用于沟槽的衬垫由半导体或金属层形成，该半导体或金属层在低温过程中沉积，这降低了锗除气。 低温过程可以是ALD过程。

公开(公告)号：US07648886B2

公开(公告)日：2010-01-19

申请号：US10341863

申请日：2003-01-14

申请人： Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

发明人： Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

IPC分类号： H01L21/762

CPC分类号： H01L21/76224

摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed to in a low temperature process which reduces germanium outgassing. The low temperature process can be a UVO, ALD, CVD, PECVD, or HDP process.

摘要翻译： 集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。 浅沟槽隔离技术用于应变硅（SMOS）工艺。 用于沟槽的衬垫形成为能够减少锗除气的低温过程。 低温过程可以是UVO，ALD，CVD，PECVD或HDP工艺。

公开(公告)号：US07238591B1

公开(公告)日：2007-07-03

申请号：US10973871

申请日：2004-10-26

申请人： Ming-Ren Lin

发明人： Ming-Ren Lin

IPC分类号： H01L21/84

CPC分类号： H01L21/76256 ,  H01L21/84 ,  Y10S438/928

摘要： A method of forming a silicon-on-insulator substrate is disclosed, including providing a silicon substrate; depositing a first insulation layer over the silicon substrate; forming a conductive layer over the first insulation layer to a first structure; providing a second structure comprising a silicon device layer and a second insulation layer; bonding the first structure and the second structure together so that the conductive layer is located between the first and second insulation layers; and removing a portion of the silicon device layer thereby providing the silicon-on-insulator substrate having two discrete insulation layers. In one embodiment, the method further includes forming at least one conductive plug through the silicon substrate and the first insulation layer and/or the second insulation layer so as to contact the conductive layer. Methods of facilitating heat removal from the device layer are disclosed.

摘要翻译： 公开了一种形成绝缘体上硅衬底的方法，包括提供硅衬底; 在所述硅衬底上沉积第一绝缘层; 在所述第一绝缘层上形成导电层至第一结构; 提供包括硅器件层和第二绝缘层的第二结构; 将第一结构和第二结构结合在一起，使得导电层位于第一和第二绝缘层之间; 以及去除硅器件层的一部分，从而提供具有两个离散绝缘层的绝缘体上硅衬底。 在一个实施例中，该方法还包括通过硅衬底和第一绝缘层和/或第二绝缘层形成至少一个导电插塞，以便与导电层接触。 公开了促进从器件层去除热的方法。

公开(公告)号：US20060099752A1

公开(公告)日：2006-05-11

申请号：US10986399

申请日：2004-11-10

申请人： Qi Xiang ,  Niraj Subba ,  Witold Maszara ,  Zoran Krivokapic ,  Ming-Ren Lin

发明人： Qi Xiang ,  Niraj Subba ,  Witold Maszara ,  Zoran Krivokapic ,  Ming-Ren Lin

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L29/66772 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/78639 ,  H01L29/78684 ,  Y10S438/938

摘要： A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.

摘要翻译： 提供了一种在绝缘体上具有半导体层的绝缘体的半导体衬底。 形成深沟槽隔离，向半导体层引入应变。 栅极电介质和栅极形成在半导体层上。 在栅极周围形成间隔物，并且将半导体层和绝缘体去除在间隔物的外部。 凹陷的源极/漏极形成在间隔物外部。

公开(公告)号：US06962857B1

公开(公告)日：2005-11-08

申请号：US10358966

申请日：2003-02-05

申请人： Minh-Van Ngo ,  Ming-Ren Lin ,  Eric N. Paton ,  Haihong Wang ,  Qi Xiang ,  Jung-Suk Goo

发明人： Minh-Van Ngo ,  Ming-Ren Lin ,  Eric N. Paton ,  Haihong Wang ,  Qi Xiang ,  Jung-Suk Goo

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L21/76224 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823878

摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in a strained silicon (SMOS) process. The liner for the trench is formed from a layer deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be an LPCVD. An annealing step can be utilized to form the liner.

摘要翻译： 集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。 浅沟槽隔离技术用于应变硅（SMOS）工艺。 用于沟槽的衬垫由沉积在低温过程中的层形成，其减少锗除气。 低温过程可以是LPCVD。 可以使用退火步骤来形成衬垫。

公开(公告)号：US06905971B1

公开(公告)日：2005-06-14

申请号：US10331938

申请日：2002-12-30

申请人： Cyrus Tabery ,  Chih-Yuh Yang ,  William G. En ,  Joong S. Jeon ,  Minh Van Ngo ,  Ming-Ren Lin

发明人： Cyrus Tabery ,  Chih-Yuh Yang ,  William G. En ,  Joong S. Jeon ,  Minh Van Ngo ,  Ming-Ren Lin

IPC分类号： H01L21/302 ,  H01L21/311 ,  H01L21/461

CPC分类号： H01L21/31116 ,  H01L21/31122

摘要： In one embodiment, the present invention relates to a method for pre-treating and etching a dielectric layer in a semiconductor device comprising the steps of: (A) pre-treating one or more exposed portions of a dielectric layer with a plasma in a plasma etching tool to increase removal rate of the one or more exposed portions upon etching; and (B) removing the one or more exposed portions of the dielectric layer in the same plasma etching tool of step (A) via plasma etching.

摘要翻译： 在一个实施例中，本发明涉及一种用于在半导体器件中预处理和蚀刻电介质层的方法，包括以下步骤：（A）用等离子体中的等离子体预处理介电层的一个或多个暴露部分 蚀刻工具，以在蚀刻时增加一个或多个暴露部分的去除速率; 和（B）通过等离子体蚀刻在步骤（A）的相同等离子体蚀刻工具中去除介电层的一个或多个暴露部分。

公开(公告)号：US06842048B2

公开(公告)日：2005-01-11

申请号：US10301617

申请日：2002-11-22

申请人： Zoran Krivokapic ,  Judy Xilin An ,  Ming-Ren Lin ,  Haihong Wang

发明人： Zoran Krivokapic ,  Judy Xilin An ,  Ming-Ren Lin ,  Haihong Wang

IPC分类号： H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786 ,  H03K19/20

CPC分类号： H01L27/1203 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/42384 ,  H01L29/785 ,  H01L29/7856

摘要： A NOR gate includes is constructed with two asymmetric FinFET type transistors instead of the conventional four-transistor NOR gate. The reduction in the number of transistors from four down to two allows for significant improvements in integrated semiconductor circuits.

摘要翻译： NOR门包括用两个非对称的FinFET型晶体管构成，而不是常规的四晶体管或非门。 晶体管数量从四个减少到二个允许集成半导体电路的显着改进。

公开(公告)号：US06619878B2

公开(公告)日：2003-09-16

申请号：US09800235

申请日：2001-03-02

申请人： Shyh-Jen Wang ,  Ming-Ren Lin ,  Shyh-Yau Wang ,  Su-Chen Chen

发明人： Shyh-Jen Wang ,  Ming-Ren Lin ,  Shyh-Yau Wang ,  Su-Chen Chen

IPC分类号： E05B908

CPC分类号： F16B2/18 ,  Y10T403/535 ,  Y10T403/7067

摘要： A fastening device includes a holding base capable of sliding or rotating on a rod or column, a driving bolt rotatably coupled with a thrusting block rotatably engaged in the holding base having a driving wedge face formed on the thrusting block, and a follower block movably reciprocating in the holding base having a follower wedge face formed on the follower block and tangentially engageable with the driving wedge face of the thrusting block; whereby upon a rotation of the driving bolt to inwardly push the thrusting block in the holding base, the follower block will be thrusted by the driving block to interfere in a rod (or column) surface for quickly, ergonomically and firmly fastening the rod (or column) within the holding base.