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    Method of manufacturing a germanosilicide and a semiconductor device having the germanosilicide
    2.
    发明申请
    Method of manufacturing a germanosilicide and a semiconductor device having the germanosilicide 审中-公开
    制造锗硅酸盐的方法和具有锗硅酸盐的半导体器件

    公开(公告)号：US20080164533A1

    公开(公告)日：2008-07-10

    申请号：US12000494

    申请日：2007-12-13

    申请人： Hyun-Deok Yang ,  Chang-wook Moon ,  Joong S. Jeon

    发明人： Hyun-Deok Yang ,  Chang-wook Moon ,  Joong S. Jeon

    IPC分类号： H01L29/49 ,  H01L21/44

    CPC分类号： H01L29/0847 ,  H01L21/28518 ,  H01L29/66628 ,  H01L29/78

    摘要： Example embodiments relate to a method of manufacturing a germanosilicide and a semiconductor device having the germanosilicide. A method according to example embodiments may include providing a substrate having at least a portion formed of silicon germanium. A metal layer may be formed on the silicon germanium. A thermal process may be performed on the substrate at a relatively high pressure to form the germanosilicide.

    摘要翻译： 示例性实施方案涉及制造锗硅酸盐的方法和具有锗硅酸盐的半导体器件。 根据示例性实施例的方法可以包括提供具有由硅锗形成的至少一部分的衬底。 可以在硅锗上形成金属层。 可以在相对较高的压力下在基材上进行热处理以形成硅酸锗。

    Method for forming a thin, high quality buffer layer in a field effect transistor and related structure
    3.
    发明授权
    Method for forming a thin, high quality buffer layer in a field effect transistor and related structure 有权
    在场效应晶体管和相关结构中形成薄的，高质量的缓冲层的方法

    公开(公告)号：US07071051B1

    公开(公告)日：2006-07-04

    申请号：US10761009

    申请日：2004-01-20

    申请人： Joong S. Jeon ,  Robert B. Clark-Phelps ,  Qi Xiang ,  Huicai Zhong

    发明人： Joong S. Jeon ,  Robert B. Clark-Phelps ,  Qi Xiang ,  Huicai Zhong

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/28194 ,  H01L29/51 ,  H01L29/513 ,  H01L29/7833

    摘要： According to one exemplary embodiment, a method for forming a field-effect transistor on a substrate comprises a step of forming a buffer layer on the substrate, where the buffer layer comprises ALD silicon dioxide. The buffer layer can be formed by utilizing a silicon tetrachloride precursor in an atomic layer deposition process, for example. The buffer layer comprises substantially no pin-hole defects and may have a thickness, for example, that is less than approximately 5.0 Angstroms. The method further comprises forming a high-k dielectric layer over the buffer layer. The high-k dielectric layer may be, for example, hafnium oxide, zirconium oxide, or aluminum oxide. According to this exemplary embodiment, the method further comprises forming a gate electrode layer over the high-k dielectric layer. The gate electrode layer may be polycrystalline silicon, for example.

    摘要翻译： 根据一个示例性实施例，在衬底上形成场效应晶体管的方法包括在衬底上形成缓冲层的步骤，其中缓冲层包含ALD二氧化硅。 例如，可以在原子层沉积工艺中利用四氯化硅前体形成缓冲层。 缓冲层基本上不包括针孔缺陷，并且可以具有例如小于约5.0埃的厚度。 该方法还包括在缓冲层上形成高k电介质层。 高k电介质层可以是例如氧化铪，氧化锆或氧化铝。 根据该示例性实施例，该方法还包括在高k电介质层上形成栅电极层。 栅电极层例如可以是多晶硅。

    Semiconductor component and method of manufacture
    4.
    发明授权
    Semiconductor component and method of manufacture 有权
    半导体元件及制造方法

    公开(公告)号：US07026211B1

    公开(公告)日：2006-04-11

    申请号：US10795890

    申请日：2004-03-08

    申请人： Rinji Sugino ,  Joong S. Jeon ,  Robert B. Ogle, Jr.

    发明人： Rinji Sugino ,  Joong S. Jeon ,  Robert B. Ogle, Jr.

    IPC分类号： H01L21/336

    CPC分类号： H01L27/115 ,  H01L27/11521

    摘要： A semiconductor component having smooth, void-free conductive layers and a method for manufacturing the semiconductor component. Surface features such as gate structures are formed on a semiconductor substrate. A layer of insulating material is formed on the gate structures and a layer of polysilicon is formed on the layer of insulating material. The layer of polysilicon is annealed in a hydrogen ambient to redistribute the silicon atoms of the polysilicon layer. Redistribution of the atoms fills voids that may be present in the layer of polysilicon and smoothes the surface of the layer of polysilicon. Another layer of polysilicon is formed over the annealed layer of polysilicon. This polysilicon layer is annealed in a hydrogen ambient to redistribute the silicon atoms and smooth the surface of the polysilicon layer, thereby forming a subsequently annealed polysilicon layer. Control gate structures are formed from the subsequently annealed polysilicon layer.

    摘要翻译： 具有光滑无空隙的导电层的半导体部件和半导体部件的制造方法。 诸如栅极结构的表面特征形成在半导体衬底上。 在栅极结构上形成绝缘材料层，在绝缘材料层上形成多晶硅层。 多晶硅层在氢环境中退火以重新分布多晶硅层的硅原子。 原子的再分布填充可能存在于多晶硅层中的空隙，并且平滑多晶硅层的表面。 在多晶硅的退火层上形成另一层多晶硅。 该多晶硅层在氢环境中退火以重新分配硅原子并平滑多晶硅层的表面，从而形成随后退火的多晶硅层。 控制栅结构由随后退火的多晶硅层形成。

    CMOS TRANSISTOR USING GERMANIUM CONDENSATION AND METHOD OF FABRICATING THE SAME
    5.
    发明申请
    CMOS TRANSISTOR USING GERMANIUM CONDENSATION AND METHOD OF FABRICATING THE SAME 有权
    使用锗浓缩的CMOS晶体管及其制造方法

    公开(公告)号：US20120214282A1

    公开(公告)日：2012-08-23

    申请号：US13462396

    申请日：2012-05-02

    申请人： Jun-youn KIM ,  Joong S. Jeon

    发明人： Jun-youn KIM ,  Joong S. Jeon

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/7848

    摘要： Provided is a CMOS transistor formed using Ge condensation and a method of fabricating the same. The CMOS transistor may include an insulating layer, a silicon layer on the insulating layer and including a p-MOS transistor region and an n-MOS transistor region, a first gate insulating layer and a first gate on a channel region of the p-MOS transistor region, and a second gate insulating layer and a second gate on a channel region of the n-MOS transistor region, wherein a source region and a drain region of the p-MOS transistor region may be tensile-strained due to Ge condensation, and the channel region of the n-MOS transistor region may be tensile-strained due to the Ge condensation.

    摘要翻译： 提供了使用Ge缩合形成的CMOS晶体管及其制造方法。 CMOS晶体管可以包括绝缘层，绝缘层上的硅层，并且包括p-MOS晶体管区域和n-MOS晶体管区域，第一栅极绝缘层和p-MOS沟道区域上的第一栅极 晶体管区域，以及在n-MOS晶体管区域的沟道区域上的第二栅极绝缘层和第二栅极，其中由于Ge冷凝，p-MOS晶体管区域的源极区域和漏极区域可能被拉伸应变， 并且由于Ge缩合，n-MOS晶体管区域的沟道区域可能被拉伸应变。

    Method of fabricating Schottky barrier transistor
    8.
    发明授权
    Method of fabricating Schottky barrier transistor 有权
    制造肖特基势垒晶体管的方法

    公开(公告)号：US07674665B2

    公开(公告)日：2010-03-09

    申请号：US12149894

    申请日：2008-05-09

    申请人： Sung-ho Park ,  Jin-seo Noh ,  Joong S. Jeon ,  Eun-ju Bae

    发明人： Sung-ho Park ,  Jin-seo Noh ,  Joong S. Jeon ,  Eun-ju Bae

    IPC分类号： H01L21/338

    CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7839

    摘要： Provided is a method of fabricating a Schottky barrier transistor. The method includes (a) forming a pair of cavities for forming a source forming portion and a drain forming portion having a predetermined depth and parallel to each other and a channel forming portion having a fin shape between the cavities in a substrate; (b) filling the pair of cavities with a metal; (c) forming a channel, a source, and a drain by patterning the channel forming portion, the source forming portion, and the drain forming portion in a direction perpendicular to a lengthwise direction of the channel forming portion; (d) sequentially forming a gate oxide layer and a gate metal layer that cover the channel, the source, and the drain on the substrate; and (e) forming a gate electrode corresponding to the channel by patterning the gate metal layer, wherein one of the operations (b) through (e) further comprises forming a Schottky barrier by annealing the substrate.

    摘要翻译： 提供了制造肖特基势垒晶体管的方法。 该方法包括：（a）形成用于形成具有预定深度并彼此平行的源极形成部分和漏极形成部分的一对空腔，以及在衬底中的空腔之间具有翅片形状的沟道形成部分; （b）用金属填充一对空腔; （c）通过在垂直于沟道形成部分的长度方向的方向上图形化沟道形成部分，源形成部分和漏极形成部分来形成沟道，源极和漏极; （d）顺序地形成覆盖衬底上的沟道，源极和漏极的栅极氧化物层和栅极金属层; 以及（e）通过对所述栅极金属层进行构图来形成对应于所述沟道的栅电极，其中，所述（b）至（e）中的一个还包括通过使所述衬底退火来形成肖特基势垒。