公开(公告)号：US07422961B2

公开(公告)日：2008-09-09

申请号：US10389456

申请日：2003-03-14

Applicant: Haihong Wang ,  Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

Inventor： Haihong Wang ,  Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/823481 ,  H01L29/1054

Abstract: A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a CVD process.

Abstract translation: 集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。 浅沟槽隔离技术用于应变硅（SMOS）工艺。 用于沟槽的衬垫由半导体或金属层形成，该半导体或金属层在低温过程中沉积，这降低了锗除气。 低温工艺可以是CVD工艺。

公开(公告)号：US20080054316A1

公开(公告)日：2008-03-06

申请号：US11926655

申请日：2007-10-29

Applicant: Qi Xiang ,  Niraj Subba ,  Witold Maszara ,  Zoran Krivokapic ,  Ming-Ren Lin

Inventor： Qi Xiang ,  Niraj Subba ,  Witold Maszara ,  Zoran Krivokapic ,  Ming-Ren Lin

IPC: H01L29/78

CPC classification number: H01L29/66772 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/78639 ,  H01L29/78684 ,  Y10S438/938

Abstract: A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.

Abstract translation: 提供了一种在绝缘体上具有半导体层的绝缘体的半导体衬底。 形成深沟槽隔离，向半导体层引入应变。 栅极电介质和栅极形成在半导体层上。 在栅极周围形成间隔物，并且将半导体层和绝缘体去除在间隔物的外部。 凹陷的源极/漏极形成在间隔物外部。

公开(公告)号：US20060177998A1

公开(公告)日：2006-08-10

申请号：US11379435

申请日：2006-04-20

Applicant: Ming-Ren Lin ,  Witold Maszara ,  Haihong Wang ,  Bin Yu

Inventor： Ming-Ren Lin ,  Witold Maszara ,  Haihong Wang ,  Bin Yu

IPC: H01L21/3205

CPC classification number: H01L29/785 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/7842

Abstract: A method may include forming a gate electrode over a fin structure, depositing a first metal layer on a top surface of the gate electrode, performing a first silicide process to convert a portion of the gate electrode into a metal-silicide compound, depositing a second metal layer on a top surface of the metal-silicide compound, and performing a second silicide process to form a fully-silicided gate electrode.

Abstract translation: 一种方法可以包括在鳍结构上形成栅电极，在栅电极的顶表面上沉积第一金属层，执行第一硅化工艺以将栅电极的一部分转化为金属硅化物， 在金属硅化物化合物的顶表面上的金属层，并且执行第二硅化物处理以形成全硅化物栅电极。

公开(公告)号：US06858503B1

公开(公告)日：2005-02-22

申请号：US10358484

申请日：2003-02-05

Applicant: Minh V. Ngo ,  Ming-Ren Lin ,  Paul R. Besser ,  Qi Xiang ,  Eric N. Paton ,  Jung-Suk Goo

Inventor： Minh V. Ngo ,  Ming-Ren Lin ,  Paul R. Besser ,  Qi Xiang ,  Eric N. Paton ,  Jung-Suk Goo

IPC: H01L21/306 ,  H01L29/10 ,  H01L21/336

CPC classification number: H01L21/02046 ,  H01L29/1054

Abstract: A fabrication system utilizes a protocol for removing germanium from a top surface of a wafer. An exposure to a gas, such as a gas containing the hydrochloric acid can remove germanium from the top surface. The protocol can allow shared equipment to be used in both Flash product fabrication lines and strained silicon (SMOS) fabrication lines. The protocol allows better silicidation in SMOS devices.

Abstract translation: 制造系统利用从晶片顶表面去除锗的方案。 暴露于气体，如含有盐酸的气体，可以从上表面除去锗。 该协议可以允许在Flash产品制造线和应变硅（SMOS）生产线中使用共享设备。 该协议允许在SMOS器件中更好的硅化。

公开(公告)号：US06764966B1

公开(公告)日：2004-07-20

申请号：US10085278

申请日：2002-02-27

Applicant: William George En ,  Arvind Halliyal ,  Ming-Ren Lin ,  Minh Van Ngo ,  Chih-Yuh Yang

Inventor： William George En ,  Arvind Halliyal ,  Ming-Ren Lin ,  Minh Van Ngo ,  Chih-Yuh Yang

IPC: H01L2128

CPC classification number: H01L29/6656 ,  H01L29/66833 ,  H01L29/78

Abstract: A semiconductor device formed on a semiconductor substrate having an active region and a method of making the same is disclosed. The semiconductor device includes a dielectric layer interposed between a gate electrode and the semiconductor substrate. Further, the semiconductor device includes graded dielectric constant spacers formed on sidewalls of the dielectric layer, sidewalls of the gate electrode and portions of an upper surface of the semiconductor substrate. The dielectric constant of the graded dielectric constant spacers decreases in a direction away from the sidewalls of the dielectric layer.

Abstract translation: 公开了一种形成在具有有源区的半导体衬底上的半导体器件及其制造方法。 半导体器件包括插入在栅电极和半导体衬底之间的电介质层。 此外，半导体器件包括形成在电介质层的侧壁，栅电极的侧壁和半导体衬底的上表面的部分上的渐变介电常数间隔物。 梯度介电常数间隔物的介电常数在远离介电层的侧壁的方向上减小。

公开(公告)号：US06670260B1

公开(公告)日：2003-12-30

申请号：US09577332

申请日：2000-05-24

Applicant: Bin Yu ,  Ming-Ren Lin ,  Shekhar Pramanick

Inventor： Bin Yu ,  Ming-Ren Lin ,  Shekhar Pramanick

IPC: H01L21425

CPC classification number: H01L29/6659 ,  H01L29/0649 ,  H01L29/78

Abstract: A thin filmed fully-depleted silicon-on-insulator (SOI) metal oxide semiconductor field defect transistor (MOSFET) utilizes a local insulation structure. The local insulative structure includes a buried silicon dioxide region under the channel region. The MOSFET body thickness is very small and yet silicon available outside of the channel region and buried silicon dioxide region is available for sufficient depths of silicide in the source and drain regions. The buried silicon dioxide region can be formed by a trench isolation technique or a LOCOS technique.

Abstract translation: 薄膜完全耗尽的绝缘体上硅（SOI）金属氧化物半导体场缺陷晶体管（MOSFET）利用局部绝缘结构。 局部绝缘结构包括沟道区下方的埋置二氧化硅区域。 MOSFET体的厚度非常小，而在沟道区域和掩埋的二氧化硅区域之外可用的硅可用于源极和漏极区域中足够的硅化物深度。 掩埋的二氧化硅区域可以通过沟槽隔离技术或LOCOS技术形成。

公开(公告)号：US06342438B2

公开(公告)日：2002-01-29

申请号：US09187379

申请日：1998-11-06

Applicant: Bin Yu ,  Ming-Ren Lin

Inventor： Bin Yu ,  Ming-Ren Lin

IPC: H01L21265

CPC classification number: H01L21/823842 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823871

Abstract: A dual doped CMOS gate structure utilizes a nitrogen implant to suppress dopant inter-diffusion. The nitrogen implant is provided above standard trench isolation structures. Alternatively, an oxygen implant can be utilized. The use of the implant allows an increase in packing density for ultra-large-scale integrated (ULSI) circuits. The doping for N-channel and P-channel active regions can be completed when the polysilicon gate structures are doped.

Abstract translation: 双掺杂CMOS栅极结构利用氮注入来抑制掺杂剂相互扩散。 在标准沟槽隔离结构之上提供氮注入。 或者，可以使用氧注入。 使用植入物可以提高超大规模集成（ULSI）电路的封装密度。 当掺杂多晶硅栅极结构时，可以完成N沟道和P沟道有源区的掺杂。

公开(公告)号：US06262456B1

公开(公告)日：2001-07-17

申请号：US09187842

申请日：1998-11-06

Applicant: Bin Yu ,  Ming-Ren Lin

Inventor： Bin Yu ,  Ming-Ren Lin

IPC: H01L31113

CPC classification number: H01L29/6659 ,  H01L21/82345 ,  H01L21/823842 ,  H01L27/0922 ,  H01L27/105 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7833

Abstract: An ultra-large-scale integrated (ULSI) circuit includes MOSFETs which have different threshold voltages and yet have the same channel characteristics. The MOSFETs include gate structures with a polysilicon material. The polysilicon material is implanted with lower concentrations of germanium where lower threshold voltage MOSFETs are required. Over a range of 0-60% concentration of germanium, the threshold voltage can be varied by roughly 240 mV.

Abstract translation: 超大规模集成（ULSI）电路包括具有不同阈值电压但具有相同通道特性的MOSFET。 MOSFET包括具有多晶硅材料的栅极结构。 用较低浓度的锗注入多晶硅材料，其中需要较低的阈值电压MOSFET。 在锗的0-60％浓度范围内，阈值电压可以改变大约240mV。

公开(公告)号：US06248675B1

公开(公告)日：2001-06-19

申请号：US09369099

申请日：1999-08-05

Applicant: Qi Xiang ,  Ming-Ren Lin

Inventor： Qi Xiang ,  Ming-Ren Lin

IPC: H01L21302

CPC classification number: H01L21/02672 ,  H01L21/02532 ,  H01L21/2022 ,  H01L21/28061 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/76229 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: A method for fabricating short channel field effect transistors with dual gates and with a gate dielectric having a high dielectric constant. The field effect transistor is initially fabricated to have a sacrificial gate dielectric and a dummy gate electrode. Any fabrication process, such as an activation anneal or a salicidation anneal of the source and drain of the field effect transistor, using relatively high temperature is performed with the field effect transistor having the sacrificial gate dielectric and the dummy gate electrode. The dummy gate electrode and the sacrificial gate dielectric are etched from the field effect transistor to form a gate opening. A layer of dielectric with high dielectric constant is deposited on the side wall and the bottom wall of the gate opening, and a crystallization enhancing layer is deposited on the bottom wall of the gate opening. Amorphous gate electrode material, such as amorphous silicon, is deposited to fill the gate opening after the crystallization enhancing layer has been deposited. Dual gates for both an N-channel field effect transistor and a P-channel field effect transistor are formed by doping the amorphous gate electrode material with an N-type dopant for an N-channel field effect transistor, and by doping the amorphous gate electrode material with a P-type dopant for a P-channel field effect transistor. The amorphous gate electrode material in the gate opening is then annealed at a relatively low temperature, such as 500° Celsius, using an enhanced crystallization process to convert the amorphous gate electrode material, such as amorphous silicon, into polycrystalline gate electrode material, such as polycrystalline silicon. Thus, relatively low temperatures are used in the present invention to preserve the integrity of the gate dielectric having the high dielectric constant.

Abstract translation: 一种用于制造具有双栅极和具有高介电常数的栅极电介质的短沟道场效应晶体管的方法。 场效应晶体管最初被制造成具有牺牲栅极电介质和虚拟栅电极。 使用具有牺牲栅极电介质和虚拟栅电极的场效应晶体管，使用相对较高的温度进行任何制造工艺，例如场效应晶体管的源极和漏极的激活退火或腐蚀退火。 从场效应晶体管蚀刻伪栅电极和牺牲栅电介质以形成栅极开口。 在栅极的侧壁和底壁上沉积具有高介电常数的电介质层，并且在栅极开口的底壁上沉积结晶增强层。 沉积结晶增强层之后，沉积非晶态栅极材料，例如非晶硅，以填充栅极开口。 通过用N型掺杂剂掺杂非晶栅电极材料来形成用于N沟道场效应晶体管和P沟道场效应晶体管的双栅极，并且通过掺杂非晶栅电极 具有用于P沟道场效应晶体管的P型掺杂剂的材料。 然后使用增强的结晶工艺在较低温度（例如500℃）下将栅极开口中的非晶栅电极材料退火，以将诸如非晶硅的非晶栅电极材料转化为多晶栅电极材料，例如 多晶硅。 因此，在本发明中使用相对较低的温度来保持具有高介电常数的栅极电介质的完整性。

公开(公告)号：US6165902A

公开(公告)日：2000-12-26

申请号：US187520

申请日：1998-11-06

Applicant: Shekhar Pramanick ,  Ming-Ren Lin ,  Qi Xiang

Inventor： Shekhar Pramanick ,  Ming-Ren Lin ,  Qi Xiang

IPC: H01L21/285 ,  H01L21/44

CPC classification number: H01L21/28518 ,  H01L21/28568

Abstract: Low resistance contacts are formed on source/drain regions and gate electrodes by selectively depositing a reaction barrier layer and selectively depositing a metal layer on the reaction barrier layer. Embodiments include selectively depositing an alloy of cobalt and tungsten which functions as a reaction barrier layer preventing silicidation of a layer of nickel or cobalt selectively deposited thereon. Embodiments also include tailoring the composition of the cobalt tungsten alloy so that a thin silicide layer is formed thereunder for reduced contact resistance.

Abstract translation: 通过选择性地沉积反应阻挡层并在反应阻挡层上选择性地沉积金属层，在源/漏区和栅电极上形成低电阻触点。 实施方案包括选择性沉积钴和钨的合金，其用作反应阻挡层，防止选择性沉积在其上的镍或钴层的硅化。 实施例还包括定制钴钨合金的组成，使得在其下形成薄的硅化物层以降低接触电阻。