公开(公告)号：US07564317B2

公开(公告)日：2009-07-21

申请号：US11773966

申请日：2007-07-06

申请人： Ming-Dou Ker ,  Hung-Tai Liao ,  Ryan Hsin-Chin Jiang

发明人： Ming-Dou Ker ,  Hung-Tai Liao ,  Ryan Hsin-Chin Jiang

IPC分类号： H03B5/36

CPC分类号： H03B5/36

摘要： A high/low voltage tolerant interface circuit and a crystal oscillator circuit using the same are provided herein. The interface circuit includes a first transistor, a bulk-voltage generator module and an bias module. The first transistor includes a gate, a first source/drain, a bulk coupled to the first source/drain of the first transistor and a second source/drain coupled to an input node. The bulk-voltage generator module is, used to determine whether a first voltage or a predetermined voltage is being provided to the bulk of the first transistor according to the voltage of the input node. The bias module is coupled to the gate of the first transistor. The bias module is used to provide an bias voltage to the gate of the first transistor and makes the first transistor conduct in order to control the voltage of the second source/drain voltage of the first transistor.

摘要翻译： 本文提供了高/低电压容限接口电路和使用其的晶体振荡器电路。 接口电路包括第一晶体管，体电压发生器模块和偏置模块。 第一晶体管包括栅极，第一源极/漏极，耦合到第一晶体管的第一源极/漏极的体，以及耦合到输入节点的第二源极/漏极。 大容量电压发生器模块用于根据输入节点的电压确定是否向第一晶体管本体提供第一电压或预定电压。 偏置模块耦合到第一晶体管的栅极。 偏置模块用于向第一晶体管的栅极提供偏置电压，并使第一晶体管导通，以便控制第一晶体管的第二源极/漏极电压的电压。

公开(公告)号：US20090179222A1

公开(公告)日：2009-07-16

申请号：US12013637

申请日：2008-01-14

申请人： Ming-Dou Ker ,  Chun-Yu Lin ,  Chang-Tzu Wang

发明人： Ming-Dou Ker ,  Chun-Yu Lin ,  Chang-Tzu Wang

IPC分类号： H01L29/747

CPC分类号： H01L29/87 ,  H01L27/0262 ,  H01L29/0626 ,  H01L29/0692

摘要： A silicon controlled rectifier structure of polygonal layouts is provided. The polygonal first conductive type doped region is located in the middle of the polygonal second conductive type well. The first conductive type well shaped as a polygonal ring surrounds the second conductive type well and the second conductive type doped region is located within the first conductive type well and shaped as a polygonal ring concentric to the first conductive type well.

摘要翻译： 提供了多边形布局的可控硅整流器结构。 多边形第一导电型掺杂区域位于多边形第二导电类型阱的中间。 良好成形为多边形环的第一导电类型围绕第二导电类型阱并且第二导电类型掺杂区域位于第一导电类型阱内并且形状为与第一导电类型阱同心的多边形环。

公开(公告)号：US07532034B2

公开(公告)日：2009-05-12

申请号：US11489325

申请日：2006-07-19

申请人： Ming-Dou Ker ,  Shih-Lun Chen

发明人： Ming-Dou Ker ,  Shih-Lun Chen

IPC分类号： H03K19/0175 ,  H03K19/00 ,  H03K10/02

CPC分类号： H03K19/018528

摘要： A mixed-voltage input/output buffer having low-voltage design comprises a pre-driver, a tracking unit, a driving unit, and input/output pad, a floating-well unit and a transporting unit. The pre-driver receives first data signal and enable signal and outputs first and second data voltages. The tracking unit provides Gate-Tracking function. The driving unit couples the pre-driver and the tracking unit for production of a first buffer voltage corresponding to the first data voltage. The input/output pad couples the driving unit to output a first buffer voltage and to receive a second data signal. The output unit is used for outputting a second buffer voltage corresponding to the second data signal. The floating-well unit couples to the driving unit and the input/output pad in order to output first buffer voltage and receive second data signal. The floating-well unit is used for preventing leakage current.

摘要翻译： 具有低电压设计的混合电压输入/输出缓冲器包括预驱动器，跟踪单元，驱动单元和输入/输出垫，浮动井单元和传送单元。 预驱动器接收第一数据信号并使能信号并输出​​第一和第二数据电压。 跟踪单元提供Gate-Tracking功能。 驱动单元耦合预驱动器和跟踪单元，用于产生对应于第一数据电压的第一缓冲电压。 输入/输出焊盘耦合驱动单元以输出第一缓冲电压并接收第二数据信号。 输出单元用于输出对应于第二数据信号的第二缓冲电压。 浮动单元耦合到驱动单元和输入/输出垫，以便输出第一缓冲电压并接收第二数据信号。 浮动井单元用于防止漏电流。

公开(公告)号：US20090096432A1

公开(公告)日：2009-04-16

申请号：US11907644

申请日：2007-10-16

申请人： Bo-Shih Huang ,  Ming-Dou Ker

发明人： Bo-Shih Huang ,  Ming-Dou Ker

IPC分类号： G05F1/70

CPC分类号： H01L27/0251

摘要： An active loading-reduction device is provided for a circuit. The circuit has functional circuitry coupled to a terminal to receive an alternating voltage. The circuit also has an electrostatic discharge protector that is coupled to the terminal. The active loading-reduction device includes active circuitry that is adapted to be coupled to a power supply to provide a reactance to counteract a reactance provided by the electrostatic discharge protector at the terminal of the circuit.

摘要翻译： 为电路提供一个有源负载减小装置。 电路具有耦合到端子以接收交流电压的功能电路。 电路还具有耦合到端子的静电放电保护器。 有源负载减小装置包括有源电路，其适于耦合到电源以提供电抗以抵消由电路端子处的静电放电保护器提供的电抗。

公开(公告)号：US20090032838A1

公开(公告)日：2009-02-05

申请号：US12113912

申请日：2008-05-01

申请人： Tang-Kuei Tseng ,  Che-Hao Chuang ,  Ryan Hsin-Chin Jiang ,  Ming-Dou Ker

发明人： Tang-Kuei Tseng ,  Che-Hao Chuang ,  Ryan Hsin-Chin Jiang ,  Ming-Dou Ker

IPC分类号： H01L29/747

CPC分类号： H01L27/0262 ,  H01L29/747 ,  H01L29/87

摘要： The present invention discloses a symmetric bidirectional silicon-controlled rectifier, which comprises: a substrate; a buried layer formed on the substrate; a first well, a middle region and a second well, which are sequentially formed on the buried layer side-by-side; a first semiconductor area and a second semiconductor area both formed inside the first well; a third semiconductor area formed in a junction between the first well and the middle region, wherein a first gate is formed over a region between the second and third semiconductor areas; a fourth semiconductor area and a fifth semiconductor area both formed inside the second well; a sixth semiconductor area formed in a junction between the second well and the middle region, wherein a second gate is formed over a region between the fifth and sixth semiconductor areas.

摘要翻译： 本发明公开了一种对称双向硅控整流器，其包括：衬底; 形成在基板上的掩埋层; 第一阱，中间区域和第二阱，并排地依次形成在掩埋层上; 第一半导体区域和第二半导体区域都形成在第一阱内; 形成在所述第一阱和所述中间区域之间的接合处的第三半导体区域，其中在所述第二和第三半导体区域之间的区域上形成第一栅极; 形成在第二阱内的第四半导体区域和第五半导体区域; 形成在所述第二阱和所述中间区域之间的接合处的第六半导体区域，其中在所述第五和第六半导体区域之间的区域上形成第二栅极。

公开(公告)号：US07397280B2

公开(公告)日：2008-07-08

申请号：US11366143

申请日：2006-03-02

申请人： Ming-Dou Ker ,  Wen-Yi Chen ,  Che-Hao Chuang

发明人： Ming-Dou Ker ,  Wen-Yi Chen ,  Che-Hao Chuang

IPC分类号： H03K19/0175

CPC分类号： H01L27/0266

摘要： A circuit for electrostatic discharge (ESD) protection includes a resistor a capacitor connected in series with the resistor, a first transistor including a gate, the gate being connected to a first power supply providing a first voltage to the gate via the resistor and a first terminal connected to the first power supply, a second transistor including a gate, the gate being connected to a second power supply, the second power supply providing a second voltage smaller than the first voltage, the second transistor having a first terminal connected to a second terminal of the first transistor, and a third transistor including a gate, the gate being connected to the second power supply, a first terminal of the third transistor being connected to a second terminal of the second transistor, and a second terminal being connected to a reference voltage different from the first voltage and the second voltage.

摘要翻译： 用于静电放电（ESD）保护的电路包括电阻器，与电阻器串联连接的电容器，包括栅极的第一晶体管，栅极连接到第一电源，通过电阻向栅极提供第一电压，第一 端子连接到第一电源，第二晶体管包括栅极，栅极连接到第二电源，第二电源提供小于第一电压的第二电压，第二晶体管具有连接到第二电源的第一端子 第一晶体管的端子和包括栅极的第三晶体管，栅极连接到第二电源，第三晶体管的第一端子连接到第二晶体管的第二端子，第二端子连接到第二晶体管， 参考电压不同于第一电压和第二电压。

公开(公告)号：US07394630B2

公开(公告)日：2008-07-01

申请号：US10268756

申请日：2002-10-11

申请人： Ming-Dou Ker ,  Kuo-Chun Hsu ,  Hsin-Chin Jiang

发明人： Ming-Dou Ker ,  Kuo-Chun Hsu ,  Hsin-Chin Jiang

IPC分类号： H02H3/22

CPC分类号： H01L27/0266

摘要： An electrostatic discharge protection circuit that includes at least two transistors connected in a stacked configuration, a first diffusion region of a first dopant type shared by two adjacent transistors, and a second diffusion region of a second dopant type formed in the first diffusion region. A substrate-triggered site is induced into the device structure of the stacked transistors to improve ESD robustness and turn-on speed. An area-efficient layout to realize the stacked transistors is proposed. The stacked transistors may be implemented in ESD protection circuits with a mixed-voltage I/O interface, or in integrated circuits with multiple power supplies. The stacked transistors are fabricated without using a thick-gate mask.

摘要翻译： 一种静电放电保护电路，其包括以堆叠结构连接的至少两个晶体管，由两个相邻晶体管共享的第一掺杂剂类型的第一扩散区域和形成在第一扩散区域中的第二掺杂剂类型的第二扩散区域。 衬底触发位置被引入堆叠晶体管的器件结构，以提高ESD稳健性和开启速度。 提出了实现堆叠晶体管的区域效率布局。 堆叠晶体管可以在具有混合电压I / O接口的ESD保护电路中或在具有多个电源的集成电路中实现。 在不使用厚栅掩模的情况下制造堆叠晶体管。

公开(公告)号：US20080151446A1

公开(公告)日：2008-06-26

申请号：US11613193

申请日：2006-12-20

申请人： Ming-Dou Ker ,  Jia-Huei Chen ,  Ryan Hsin-Chin Jiang

发明人： Ming-Dou Ker ,  Jia-Huei Chen ,  Ryan Hsin-Chin Jiang

IPC分类号： H02H9/00

CPC分类号： H01L27/027 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrostatic discharge (ESD) protection device and a layout thereof are provided. A bias conducting wire is mainly used to couple each base of a plurality of parasitic transistors inside ESD elements together, in order to simultaneously trigger all the parasitic transistors to bypass the ESD current, avoid the elements of a core circuit being damaged, and solve the non-uniform problem of bypassing the ESD current when ESD occurs. Furthermore, in the ESD protection layout, it only needs to add another doped region on a substrate neighboring to, but not contacting, doped regions of the ESD protection elements and use contacts to connect the added doped region, so as to couple each base of the parasitic transistors together without requiring for additional layout area.

摘要翻译： 提供静电放电（ESD）保护装置及其布局。 偏置导线主要用于将ESD元件内的多个寄生晶体管的每个基极耦合在一起，以便同时触发所有寄生晶体管绕过ESD电流，避免核心电路的元件被损坏，并解决 当ESD发生时绕过ESD电流的非均匀问题。 此外，在ESD保护布局中，仅需要在与ESD保护元件的掺杂区域相邻但不接触的衬底上添加另一个掺杂区域，并使用触点来连接所添加的掺杂区域，以便将 寄生晶体管一起而不需要额外的布局区域。

公开(公告)号：US20080094533A1

公开(公告)日：2008-04-24

申请号：US11894577

申请日：2007-08-21

申请人： Ming-Dou Ker ,  Chih-Kang Deng ,  Wein-Town Sun

发明人： Ming-Dou Ker ,  Chih-Kang Deng ,  Wein-Town Sun

IPC分类号： G02F1/1333 ,  H01L21/332 ,  H01L29/04

CPC分类号： H01L29/7436 ,  G02F1/136204 ,  H01L27/0248 ,  H01L27/0292

摘要： An electrostatic discharge protection device, an electrostatic discharge protection structure, and a manufacturing process of the device are provided. The electrostatic discharge protection device includes at least four doping regions, wherein two adjacent regions are of different types. The electrostatic discharge protection structure includes an electrostatic discharge bus, a plurality of first electrostatic discharge protection devices connecting to the gates of the display transistors and the electrostatic discharge bus, a plurality of second electrostatic discharge protection devices connecting to the source/drain of the transistors and the electrostatic discharge bus, and a plurality of third electrostatic discharge protection devices connecting to the input/output terminals of the drive circuit of the display and the electrostatic discharge bus.

摘要翻译： 提供静电放电保护装置，静电放电保护结构以及该装置的制造过程。 静电放电保护装置包括至少四个掺杂区域，其中两个相邻区域是不同类型的。 静电放电保护结构包括静电放电总线，连接到显示晶体管和静电放电总线的栅极的多个第一静电放电保护器件，连接到晶体管的源极/漏极的多个第二静电放电保护器件 和静电放电总线，以及连接到显示器的驱动电路的输入/输出端子和静电放电总线的多个第三静电放电保护器件。

公开(公告)号：US20080061832A1

公开(公告)日：2008-03-13

申请号：US11649551

申请日：2007-01-03

申请人： Fang-Ling Hu ,  Ming-Dou Ker

发明人： Fang-Ling Hu ,  Ming-Dou Ker

IPC分类号： H03K19/094

CPC分类号： H03K19/00361 ,  H03K19/094

摘要： A circuit configured for providing hot-carrier effect protection, the circuit comprising a first transistor including a first terminal and a second terminal, the first terminal being coupled to a conductive pad, a switch device including a terminal coupled to the conductive pad, and a control circuit configured for keeping the switch at an off state during a receiving mode at which a signal of a first voltage level or a reference level is received at the conductive pad, keeping the switch at the off state during a transmitting mode from which a signal of a second voltage level or the reference level is transmitted at the conductive pad, and keeping the switch at an on state during a transition from the receiving mode when receiving a signal of the first voltage level to the transmitting mode when transmitting a signal having the reference voltage level, wherein during the transition a voltage across the first terminal and the second terminal of the first transistor is maintained at a level below approximately the first voltage level minus the second voltage level.

摘要翻译： 一种配置用于提供热载体效应保护的电路，该电路包括第一晶体管，其包括第一端子和第二端子，第一端子耦合到导电焊盘，开关器件包括耦合到导电焊盘的端子，以及 控制电路，被配置为在接收模式期间将开关保持在断开状态，在接收模式期间，在导电焊盘处接收到第一电压电平或参考电平的信号，在发送模式期间将开关保持在断开状态， 第二电压电平或参考电平在导电焊盘处发送，并且在从接收模式转变期间将开关保持在接通状态，当在发送具有第一电压电平的信号时，当接收到第一电压电平的信号到发送模式时 参考电压电平，其中在转变期间，跨越第一晶体管的第一端子和第二端子的电压保持在a1 电平低于大约第一电压电平减去第二电压电平。