公开(公告)号：US06469385B1

公开(公告)日：2002-10-22

申请号：US09874175

申请日：2001-06-04

申请人： Steven C. Avanzino ,  Pin-Chin Connie Wang ,  Minh Van Ngo

发明人： Steven C. Avanzino ,  Pin-Chin Connie Wang ,  Minh Van Ngo

IPC分类号： H01L23522

CPC分类号： H01L23/5329 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76841 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A dielectric layer formed over the semiconductor substrate has an opening provided therein. The dielectric layer is of non-barrier dielectric material capable of being changed into a barrier dielectric material. The dielectric layer around the opening is changed into the barrier dielectric material and the conductor core material is deposited to fill the opening. The conductor core is processed to form a channel for the integrated circuit.

摘要翻译： 提供了具有半导体器件的半导体衬底的集成电路及其制造方法。 形成在半导体衬底上的电介质层具有设置在其中的开口。 电介质层是能够改变为阻挡介电材料的非阻挡介电材料。 开口周围的电介质层变成阻挡电介质材料，并且沉积导体芯材以填充开口。 处理导体芯以形成用于集成电路的通道。

公开(公告)号：US06459155B1

公开(公告)日：2002-10-01

申请号：US09729528

申请日：2000-12-05

申请人： Ramkumar Subramanian ,  Dawn M. Hopper ,  Minh Van Ngo

发明人： Ramkumar Subramanian ,  Dawn M. Hopper ,  Minh Van Ngo

IPC分类号： H01L214763

CPC分类号： H01L21/76829 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/76807

摘要： The dimensional accuracy of trench formation and, hence, metal line width, in damascene technology is improved by employing a low Si—SiON etch stop layer/ARC with reduced etch selectivity with respect to the overlying dielectric material but having a reduced extinction coefficient (k). Embodiments include via first-trench last dual damascene techniques employing a low Si—SiON middle etch stop layer/ARC having an extinction coefficient of about −0.3 to about −0.6, e.g., about −0.35, with reduced silicon and increased oxygen vis-à-vis a SiON etch stop layer having an extinction coefficient of about −1.1. Embodiments also include removing about 60% to about 90% of the low Si—SiON etch stop layer/ARC during trench formation, thereby reducing capacitance.

摘要翻译： 通过使用低Si-SiON蚀刻停止层/ ARC，相对于上覆电介质材料具有降低的蚀刻选择性但具有降低的消光系数（k（k）），改善了镶嵌技术中沟槽形成的尺寸精度以及因此金属线宽度 ）。 实施例包括通过第一沟槽最后的双镶嵌技术，其使用具有约-0.3至约-0.6，例如约-0.35的消光系数的低Si-SiON中间蚀刻停止层/ ARC，其中还原的硅和增加的氧相对于 - 具有约-1.1的消光系数的SiON蚀刻停止层。 实施例还包括在沟槽形成期间去除约60％至约90％的低Si-SiON蚀刻停止层/ ARC，从而降低电容。

公开(公告)号：US06383950B1

公开(公告)日：2002-05-07

申请号：US09974568

申请日：2001-10-10

申请人： Suzette K. Pangrle ,  Minh Van Ngo ,  Susan Tovar

发明人： Suzette K. Pangrle ,  Minh Van Ngo ,  Susan Tovar

IPC分类号： H01L21469

CPC分类号： H01L21/76801 ,  H01L21/76829

摘要： An insulating and capping structure of an integrated circuit is formed on a semiconductor wafer. An insulating layer is formed on the semiconductor wafer, and the insulating layer is comprised of a dielectric material having a low dielectric constant that is less than about 4.0 and having chemical bonds that are chemically reactive with a predetermined reactant. A reaction barrier layer is formed on the insulating layer, and the reaction barrier layer is comprised of a material that is not chemically reactive with the predetermined reactant. A capping layer is formed on the reaction barrier layer, and the capping layer is formed using the predetermined reactant. The reaction barrier layer prevents contact of the predetermined reactant with the insulating layer to prevent reaction of the predetermined reactant with the chemical bonds of the dielectric material of the insulating layer that are chemically reactive with the predetermined reactant such that the low dielectric constant of the dielectric material of the insulating layer is not increased by the formation of the capping layer. The present invention may be used to particular advantage when the predetermined reactant used for forming the capping layer and that is reactive with the insulating layer is oxygen plasma and when the reaction barrier layer is comprised of silicon nitride.

摘要翻译： 在半导体晶片上形成集成电路的绝缘和封盖结构。 在半导体晶片上形成绝缘层，绝缘层由具有小于约4.0的低介电常数且具有与预定反应物发生化学反应的化学键的电介质材料构成。 在绝缘层上形成反应阻挡层，反应阻挡层由与预定反应物不具有化学反应性的材料构成。 在反应阻挡层上形成覆盖层，使用规定的反应物形成覆盖层。 反应阻挡层防止预定反应物与绝缘层的接触，以防止预定反应物与绝缘层的电介质材料与预定反应物发生化学反应的化学键的反应，使得电介质的低介电常数 通过形成覆盖层，绝缘层的材料不会增加。 当用于形成覆盖层并且与绝缘层反应的预定反应物是氧等离子体和当反应阻挡层由氮化硅构成时，本发明可以特别有用。

公开(公告)号：US06380067B1

公开(公告)日：2002-04-30

申请号：US09588119

申请日：2000-05-31

申请人： Ramkumar Subramanian ,  Minh Van Ngo ,  Suzette K. Pangrle ,  Kashmir Sahota ,  Christopher F. Lyons

发明人： Ramkumar Subramanian ,  Minh Van Ngo ,  Suzette K. Pangrle ,  Kashmir Sahota ,  Christopher F. Lyons

IPC分类号： H01L21302

CPC分类号： H01L21/76895 ,  H01L21/0276 ,  H01L21/76802 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11534

摘要： The present invention provides a method for manufacturing a semiconductor device with a bottom anti-reflective coating (BARC) that acts as an etch stop layer and does not need to be removed. In one embodiment, electrical devices are formed on a semiconductor substrate. Contacts are then formed for each electrical device and a partially UV transparent BARC is then deposited. An inter-layer dielectric (ILD) layer is then formed and then covered with photoresist. A top ARC (TARC) is then added and the photoresist is then photolithographically processed and subsequently developed. The TARC, ILD, and BARC layers are then selectively etched down to the device contacts forming local interconnects. The photoresist and TARC are later removed, but the BARC does not require removal due to its optical transparency.

摘要翻译： 本发明提供一种用于制造半导体器件的方法，该半导体器件具有用作蚀刻停止层并且不需要去除的底部抗反射涂层（BARC）。 在一个实施例中，电子器件形成在半导体衬底上。 然后为每个电气设备形成触点，然后沉积部分UV透明的BARC。 然后形成层间电介质（ILD）层，然后用光致抗蚀剂覆盖。 然后加入顶部ARC（TARC），然后对光致抗蚀剂进行光刻处理并随后显影。 然后将TARC，ILD和BARC层选择性地刻蚀成形成局部互连的器件触点。 光致抗蚀剂和TARC随后被去除，但由于其光学透明性，BARC不需要去除。

公开(公告)号：US06335283B1

公开(公告)日：2002-01-01

申请号：US09477719

申请日：2000-01-05

申请人： Minh Van Ngo ,  Takeshi Nogami

发明人： Minh Van Ngo ,  Takeshi Nogami

IPC分类号： H01L2144

CPC分类号： H01L21/76834 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76883

摘要： Cu diffusion between Cu and Cu alloy interconnect members, e.g., lines, in a silicon oxide inter-layer dielectric is avoided or substantially reduced by converting an upper portion of the silicon oxide inter-layer dielectric between neighboring lines to silicon oxynitride and then depositing a capping layer. Embodiments include filling damascene trenches in a silicon oxide inter-layer dielectric with Cu or a Cu alloy, CMP to effect planarization such that the upper surfaces of the lines are substantially coplanar with the upper surface of the inter-layer dielectric and treating the exposed surfaces with a nitrogen plasma of sufficient strength to ion bombard the exposed inter line silicon oxide with nitrogen, thereby converting the upper portion to silicon oxynitride, while simultaneously removing or substantially reducing surface oxides on the lines. A silicon nitride capping layer is then deposited.

摘要翻译： 通过将相邻线路之间的氧化硅层间电介质的上部部分转换为氮氧化硅，然后沉积氧化硅层，从而避免或基本上减少氧化硅层间电介质中Cu和Cu合金互连构件（例如线）之间的Cu扩散 盖层 实施例包括用Cu或Cu合金填充氧化硅层间电介质中的镶嵌沟槽CMP，以实现平面化，使得线的上表面与层间电介质的上表面基本上共面并且处理暴露表面 具有足够强度的氮等离子体用氮气轰击暴露的线间氧化硅，从而将上部部分转化为氮氧化硅，同时除去或基本上还原管线上的表面氧化物。 然后沉积氮化硅覆盖层。

公开(公告)号：US06329701B1

公开(公告)日：2001-12-11

申请号：US09411243

申请日：1999-10-04

申请人： Minh Van Ngo ,  Fei Wang

发明人： Minh Van Ngo ,  Fei Wang

IPC分类号： H01L2906

CPC分类号： H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Cu diffusion between Cu and/or Cu alloy interconnect members, e.g., lines, is avoided or substantially reduced by removing an upper portion of the inter-layer dielectric between neighboring lines to form a recess and depositing a diffusion barrier layer filling the recess between neighboring lines. Interconnects in accordance with embodiments of the present invention include Cu and/or Cu filled damascene trenches in a silicon oxide inter-layer dielectric oxide with a recess between neighboring lines filled with a silicon nitride capping layer.

摘要翻译： Cu和/或Cu合金互连构件（例如线）之间的Cu扩散通过去除相邻线之间的层间电介质的上部以形成凹部并且在相邻的线之间沉积填充凹部的扩散阻挡层而避免或基本上减少 线条。 根据本发明的实施例的互连件包括在氧化硅层间电介质氧化物中的Cu和/或Cu填充的镶嵌沟槽，其中填充有氮化硅覆盖层的相邻线之间的凹槽。

公开(公告)号：US06303505B1

公开(公告)日：2001-10-16

申请号：US09112472

申请日：1998-07-09

申请人： Minh Van Ngo ,  Shekhar Pramanick ,  Takeshi Nogami

发明人： Minh Van Ngo ,  Shekhar Pramanick ,  Takeshi Nogami

IPC分类号： H01L2144

CPC分类号： H01L21/76849 ,  H01L21/76838 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Capping layer adhesion to a Cu or Cu alloy interconnect member is enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member with a hydrogen plasma to substantially reduce oxides thereon, forming a thin layer of copper silicide on the treated surface and depositing the capping layer thereon. Embodiments include electroplating or electroless plating Cu or a Cu alloy to fill a damascene opening in a dielectric layer, chemical-mechianiical polishing, hydrogen plasma treatment, reacting the treated surface with silane or dichlorosilane to form a layer of copper silicide on the treated surface and depositing a silicon nitride capping layer on the thin copper silicide layer.

摘要翻译： 通过用氢等离子体处理Cu或Cu合金互连构件的暴露表面以大大减少其上的氧化物，在处理过的表面上形成薄的硅化铜层，并沉积到Cu或Cu合金互连构件上， 盖层。 实施例包括电镀或化学镀Cu或Cu合金以填充电介质层中的镶嵌开口，化学机械抛光，氢等离子体处理，使经处理的表面与硅烷或二氯硅烷反应，以在被处理的表面上形成硅化铜层， 在薄的硅化铜层上沉积氮化硅覆盖层。

公开(公告)号：US06294460B1

公开(公告)日：2001-09-25

申请号：US09586254

申请日：2000-05-31

申请人： Ramkumar Subramanian ,  Minh Van Ngo ,  Suzette K. Pangrle ,  Kashmir Sahota

发明人： Ramkumar Subramanian ,  Minh Van Ngo ,  Suzette K. Pangrle ,  Kashmir Sahota

IPC分类号： H01L214763

CPC分类号： H01L21/7688 ,  H01L21/76802 ,  Y10S438/952

摘要： A method is provided for manufacturing a semiconductor with fewer steps and minimized variation in the etching process by using SiON as a bottom antireflective (BARC) layer and hard mask in conjunction with a thin photoresist layer. In one embodiment, an etch-stop layer is deposited on a semiconductor substrate, a dielectric layer is deposited on top of the etch-stop layer, and a BARC is deposited on top of the dielectric layer. The BARC is deposited by PECVD to enrich the BARC with semiconductor material to increase the extinction coefficient of the BARC so its thickness can be reduced. A photoresist layer with a thickness less than the thickness of the BARC is then deposited on top of the BARC. The photoresist is then patterned, photolithographically processed, developed, and removed. The BARC is then etched away in the pattern developed on the photoresist and the photoresist is then removed. The BARC is then used as a mask for the etching of the dielectric layer. A conductive material is deposited over the BARC and the dielectric layer and is subsequently removed in the process of polishing the conductive material without requiring a separate BARC removal step.

摘要翻译： 提供了一种通过使用SiON作为底部抗反射（BARC）层和与薄的光致抗蚀剂层结合的硬掩模来制造具有较少步骤和最小化蚀刻工艺的半导体的方法。 在一个实施例中，蚀刻停止层沉积在半导体衬底上，电介质层沉积在蚀刻停止层的顶部，并且BARC沉积在电介质层的顶部上。 BARC通过PECVD沉积，以使BARC富集半导体材料，以增加BARC的消光系数，从而减小其厚度。 然后将厚度小于BARC的厚度的光致抗蚀剂层沉积在BARC的顶部。 然后将光致抗蚀剂图案化，光刻加工，显影和除去。 然后将BARC以在光致抗蚀剂上显影的图案蚀刻掉，然后除去光致抗蚀剂。 然后将BARC用作蚀刻电介质层的掩模。 导电材料沉积在BARC和电介质层上，随后在抛光导电材料的过程中被去除，而不需要单独的BARC去除步骤。

公开(公告)号：US06281584B1

公开(公告)日：2001-08-28

申请号：US09373482

申请日：1999-08-12

申请人： Minh Van Ngo ,  Richard J. Huang ,  Guarionex Morales

发明人： Minh Van Ngo ,  Richard J. Huang ,  Guarionex Morales

IPC分类号： H01L2348

CPC分类号： H01L21/31629 ,  H01L21/76801 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for using low dielectric SiOF in a process to manufacture semiconductor products, comprising the steps of obtaining a layer of SiOF, and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing ammonia. It is further preferred that the treated surface be passivated by a nitrite plasma. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielectric layer includes a first region at one edge thereof which is depleted of fluorine to a predetermined depth.

摘要翻译： 一种在制造半导体产品的方法中使用低电介质SiOF的方法，包括以下步骤：获得SiOF层，并从SiOF层的表面上消耗氟。 在优选的实施方案中，耗尽步骤包括用含有氨的等离子体处理SiOF层的表面的步骤。 进一步优选的是，经过处理的表面被亚硝酸盐等离子体钝化。 本发明还包括半导体芯片，其包括具有至少第一和第二层的集成电路，以及设置在层之间的SiOF的半导体层，其中SiOF电介质层包括其一个边缘处的第一区域，该第一区域耗尽氟 到预定深度。

公开(公告)号：US06261952B1

公开(公告)日：2001-07-17

申请号：US09411245

申请日：1999-10-04

申请人： Minh Van Ngo ,  Fei Wang

发明人： Minh Van Ngo ,  Fei Wang

IPC分类号： H01L2144

CPC分类号： H01L21/02074 ,  H01L21/31111 ,  H01L21/32136 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Cu diffusion between Cu and Cu alloy interconnect members, e.g., lines, is avoided or substantially reduced by selectively removing an upper portion of the inter-layer dielectric between neighboring lines to form a recess and depositing a diffusion barrier layer filling the recess between neighboring lines. Embodiments include filling damascene trenches in a silicon oxide inter-layer dielectric with Cu or a Cu alloy, CMP to effect planarization such that the upper surfaces of the lines are substantially coplanar with the upper surface of the inter-layer dielectric, and double-sided brush scrubbing with water. The planarized surface is then etched, as by treatment with a HF solution, to selectively remove silicon oxide between neighboring lines to form a recess therebetween. The exposed surfaces of the neighboring lines are then treated with an ammonia plasma to remove or substantially reduce oxides and a silicon nitride diffusion barrier layer is deposited on the neighboring lines filling the recesses between neighboring lines.

摘要翻译： 通过选择性地除去相邻线之间的层间电介质的上部以形成凹陷并且沉积填充相邻线之间的凹槽的扩散阻挡层，可避免或大大减少Cu和Cu合金互连构件（例如线）之间的Cu扩散 。 实施例包括在Cu或Cu合金的氧化硅层间电介质中填充镶嵌沟槽，CMP以实现平面化，使得线的上表面与层间电介质的上表面基本共面，并且双面 用水刷洗。 然后通过用HF溶液处理来蚀刻平坦化表面以选择性地除去相邻线之间的氧化硅以在它们之间形成凹陷。 然后用氨等离子体处理相邻线的暴露表面以去除或基本上减少氧化物，并且在填充相邻线之间的凹部的相邻线上沉积氮化硅扩散阻挡层。