Hybrid Memory Cell for Spin-Polarized Electron Current Induced Switching and Writing/Reading Process Using Such Memory Cell
    81.
    发明申请
    Hybrid Memory Cell for Spin-Polarized Electron Current Induced Switching and Writing/Reading Process Using Such Memory Cell 有权
    用于旋转极化电子电流的混合存储单元使用这种存储单元的切换和写入/读取过程

    公开(公告)号:US20080094881A1

    公开(公告)日:2008-04-24

    申请号:US11845525

    申请日:2007-08-27

    IPC分类号: G11C11/00

    CPC分类号: G11C11/16

    摘要: A magnetoresistive hybrid memory cell includes first and second stacked structures. The first stacked structure includes a magnetic tunnel junction including first and second magnetic regions stacked in a parallel, overlying relationship separated by a layer of non-magnetic material, wherein the first magnetic region has a fixed first magnetic moment vector and the second magnetic region has a free second magnetic moment vector that is switchable between the same and opposite directions with respect to the fixed first magnetic moment vector. The second stacked structure is at least partly arranged in a lateral relationship with respect to the first stacked structure and includes a third magnetic region having a fixed third magnetic moment vector and the second magnetic region. The first and second structures are arranged between at least two electrodes in electrical contact therewith.

    摘要翻译: 磁阻混合存储单元包括第一和第二堆叠结构。 第一堆叠结构包括磁隧道结,该磁隧道结包括由非磁性材料层隔开的并联叠置的堆叠的第一和第二磁区,其中第一磁区具有固定的第一磁矩矢量,第二磁区具有 相对于固定的第一磁矩矢量可在相同和相反方向之间切换的自由的第二磁矩矢量。 第二堆叠结构至少部分地相对于第一堆叠结构布置在横向关系中,并且包括具有固定的第三磁矩矢量和第二磁性区域的第三磁性区域。 第一和第二结构布置在与其接触的至少两个电极之间。

    Shared ground contact isolation structure for high-density magneto-resistive RAM
    82.
    发明申请
    Shared ground contact isolation structure for high-density magneto-resistive RAM 审中-公开
    用于高密度磁阻RAM的共享接地隔离结构

    公开(公告)号:US20070296007A1

    公开(公告)日:2007-12-27

    申请号:US11369195

    申请日:2006-03-06

    IPC分类号: H01L29/772 G11C11/00

    摘要: A buried ground contact that connects the ground electrodes of transistors in adjacent memory cells that are separated by an isolation region is described. In some embodiments, the buried ground contact passes beneath the isolation region that separates cells to electrically connect the drain regions of transistors in adjacent cells. The buried ground may be connected to a metal ground line through via connections at intervals, outside of the active cell area. Use of this buried ground contact eliminates the need for individual ground connections to each cell, leading to a substantial reduction in cell size, and a consequent increase in cell density. The buried ground contacts of the invention can be used with a variety of devices, including MRAM and PCRAM devices.

    摘要翻译: 描述了连接由隔离区分隔开的相邻存储单元中的晶体管的接地电极的埋地接地触点。 在一些实施例中,埋地接触通过隔离单元的隔离区下方,以电连接相邻单元中的晶体管的漏极区。 埋地可以在活动单元区域之外的间隔通过连接连接到金属接地线。 使用这种埋地接触消除了对每个电池的单独接地连接的需要,导致电池尺寸的显着降低,并且随之而来的电池密度增加。 本发明的埋地触点可以与各种装置一起使用,包括MRAM和PCRAM装置。

    MRAM memory cell with a reference layer and method for fabricating
    83.
    发明授权
    MRAM memory cell with a reference layer and method for fabricating 有权
    具有参考层的MRAM存储单元及其制造方法

    公开(公告)号:US07309617B2

    公开(公告)日:2007-12-18

    申请号:US10509553

    申请日:2003-03-11

    IPC分类号: H01L21/00

    摘要: The invention relates to a method for fabricating a reference layer for MRAM memory cells and an MRAM memory cell equipped with a reference layer of this type. A reference layer of this type comprises two magnetically coupled layers having a different Curie temperature. When cooling from a temperature above the Curie temperature TC1 of the first layer in an external magnetic field, the magnetization of the second layer is oriented by a second-order phase transition along the field direction of the external magnetic field. Upon further cooling below the Curie temperature TC2 of the second layer, the latter is oriented antiparallel with respect to the first layer as a result of the antiferromagnetic coupling between the two layers.

    摘要翻译: 本发明涉及一种用于制造用于MRAM存储器单元的参考层的方法和配备有这种类型的参考层的MRAM存储单元。 这种类型的参考层包括具有不同居里温度的两个磁耦合层。 当在外部磁场中从高于第一层的居里温度T SUB 1 SUP的温度冷却时,第二层的磁化取向为二阶相 沿着外部磁场的场方向的过渡。 当进一步冷却到低于第二层的居里温度T 2 C 2 O 2时,后者由于两者之间的反铁磁耦合而相对于第一层反向平行 层。

    MRAM structure using sacrificial layer for anti-ferromagnet and method of manufacture
    84.
    发明申请
    MRAM structure using sacrificial layer for anti-ferromagnet and method of manufacture 有权
    用于抗铁磁体的牺牲层的MRAM结构及其制造方法

    公开(公告)号:US20070278602A1

    公开(公告)日:2007-12-06

    申请号:US11448170

    申请日:2006-06-06

    IPC分类号: H01L43/00

    CPC分类号: H01L43/08 H01L43/12

    摘要: A magnetic random access memory structure comprising an anti-ferromagnetic layer structure, a crystalline ferromagnetic structure physically coupled to the anti-ferromagnetic layer structure and a ferromagnetic free layer structure physically coupled to the crystalline ferromagnetic structure.

    摘要翻译: 磁性随机存取存储器结构包括反铁磁层结构,物理耦合到反铁磁层结构的结晶铁磁结构和物理耦合到结晶铁磁结构的铁磁自由层结构。

    Techniques for reducing neel coupling in toggle switching semiconductor devices
    85.
    发明申请
    Techniques for reducing neel coupling in toggle switching semiconductor devices 失效
    用于减少拨动开关半导体器件中的神经耦合的技术

    公开(公告)号:US20050285168A1

    公开(公告)日:2005-12-29

    申请号:US10878156

    申请日:2004-06-28

    IPC分类号: H01F10/32 H01L29/76 H01L43/08

    摘要: The present invention provides techniques for data storage. In one aspect of the invention, a semiconductor device is provided. The semiconductor device comprises at least one free layer and at least one fixed layer, with at least one barrier layer therebetween. At least one pinned magnetic layer is separated from the at least one free layer by at least one non-magnetic layer, the at least one pinned magnetic layer and non-magnetic layer being configured to cancel out at least a portion of a Neel coupling between the at least one free layer and the at least one fixed layer.

    摘要翻译: 本发明提供数据存储技术。 在本发明的一个方面,提供一种半导体器件。 半导体器件包括至少一个自由层和至少一个固定层,其间具有至少一个阻挡层。 至少一个钉扎磁性层通过至少一个非磁性层与至少一个自由层分开,所述至少一个被钉扎的磁性层和非磁性层被构造成抵消了至少一部分Neel耦合 所述至少一个自由层和所述至少一个固定层。

    Method for producing a reference layer and an mram memory cell provided with said type of reference layer
    86.
    发明申请
    Method for producing a reference layer and an mram memory cell provided with said type of reference layer 有权
    用于制造参考层的方法和具有所述类型的参考层的mram存储单元

    公开(公告)号:US20050208680A1

    公开(公告)日:2005-09-22

    申请号:US10509553

    申请日:2003-03-11

    摘要: The invention relates to a method for fabricating a reference layer for MRAM memory cells and an MRAM memory cell equipped with a reference layer of this type. A reference layer of this type comprises two magnetically coupled layers having a different Curie temperature. When cooling from a temperature above the Curie temperature TC1 of the first layer in an external magnetic field, the magnetization of the second layer is oriented by a second-order phase transition along the field direction of the external magnetic field. Upon further cooling below the Curie temperature TC2 of the second layer, the latter is oriented antiparallel with respect to the first layer as a result of the antiferromagnetic coupling between the two layers.

    摘要翻译: 本发明涉及一种用于制造用于MRAM存储器单元的参考层的方法和配备有这种类型的参考层的MRAM存储单元。 这种类型的参考层包括具有不同居里温度的两个磁耦合层。 当在外部磁场中从高于第一层的居里温度T SUB 1 SUP的温度冷却时,第二层的磁化取向为二阶相 沿着外部磁场的场方向的过渡。 当进一步冷却到低于第二层的居里温度T 2 C 2 O 2时,后者由于两者之间的反铁磁耦合而相对于第一层反向平行 层。

    Small, scalable resistive element and method of manufacturing
    87.
    发明申请
    Small, scalable resistive element and method of manufacturing 审中-公开
    小型,可扩展的电阻元件和制造方法

    公开(公告)号:US20050014342A1

    公开(公告)日:2005-01-20

    申请号:US10622422

    申请日:2003-07-18

    摘要: An improved scalable, resistive element for use in a semiconductor device that can be produced with a small feature size and precise resistance is provided by the present invention. The resistive element includes a base layer positioned on top of a metal line. A seed layer of is deposited on top of the base layer. A thin barrier layer of Al is deposited on top of the seed layer and oxidized. A non-magnetic metal layer is then deposited on top of the barrier layer. The base layer and the non-magnetic metal layer form electrodes on either side of the barrier layer. The barrier layer is thin enough that a tunneling current can travel between the electrodes. The resulting resistive element may be constructed with a high resistance and a very small feature size.

    摘要翻译: 通过本发明提供了一种用于半导体器件的改进的可扩展的电阻元件,其可以以小的特征尺寸和精确的电阻产生。 电阻元件包括位于金属线顶部的基层。 种子层沉积在基层的顶部。 Al的薄势垒层沉积在种子层的顶部并被氧化。 然后将非磁性金属层沉积在阻挡层的顶部上。 基极层和非磁性金属层在势垒层的两侧形成电极。 阻挡层足够薄,使得隧道电流可以在电极之间行进。 所得到的电阻元件可以被构造成具有高电阻和非常小的特征尺寸。