High-voltage vertical transistor with a multi-gradient drain doping profile
    81.
    发明授权
    High-voltage vertical transistor with a multi-gradient drain doping profile 有权
    具有多梯度漏极掺杂特性的高压垂直晶体管

    公开(公告)号:US07791132B2

    公开(公告)日:2010-09-07

    申请号:US12655697

    申请日:2010-01-04

    IPC分类号: H01L29/772

    摘要: A high-voltage transistor includes first and second trenches that define a mesa in a semiconductor substrate. First and second field plate members are respectively disposed in the first and second trenches, with each of the first and second field plate members being separated from the mesa by a dielectric layer. The mesa includes a plurality of sections, each section having a substantially constant doping concentration gradient, the gradient of one section being at least 10% greater than the gradient of another section. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

    摘要翻译: 高压晶体管包括在半导体衬底中限定台面的第一和第二沟槽。 第一和第二场板构件分别设置在第一和第二沟槽中,第一和第二场板构件中的每一个通过介电层与台面分离。 台面包括多个部分,每个部分具有基本上恒定的掺杂浓度梯度,一个部分的梯度比另一部分的梯度大至少10%。 要强调的是,该摘要被提供以符合要求抽象的规则,允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是,它不会用于解释或限制权利要求的范围或含义。

    Method of forming lateral trench MOSFET with direct trench polysilicon contact
    82.
    发明授权
    Method of forming lateral trench MOSFET with direct trench polysilicon contact 有权
    形成具有直接沟槽多晶硅接触的横向沟槽MOSFET的方法

    公开(公告)号:US07759200B2

    公开(公告)日:2010-07-20

    申请号:US12387180

    申请日:2009-04-29

    IPC分类号: H01L21/336

    摘要: A lateral trench MOSFET includes a trench containing a device segment and a gate bus segment. The gate bus segment of the trench is contacted by a conductive plug formed in a dielectric layer overlying the substrate, thereby avoiding the need for the conventional surface polysilicon bridge layer. The conductive plug is formed in a substantially vertical hole in the dielectric layer. The gate bus segment may be wider than the device segment of the trench. A method includes forming a shallow trench isolation (STI) while the conductive material in the trench is etched.

    摘要翻译: 横向沟槽MOSFET包括包含器件段和栅极总线段的沟槽。 沟槽的栅极总线段由覆盖在衬底上的电介质层中形成的导电插塞接触,从而避免了对传统表面多晶硅桥接层的需要。 导电插塞形成在电介质层中的大致垂直的孔中。 栅极总线段可以比沟槽的器件段宽。 一种方法包括在蚀刻沟槽中的导电材料的同时形成浅沟槽隔离(STI)。

    Method of fabricating a high-voltage transistor with an extended drain structure
    83.
    发明授权
    Method of fabricating a high-voltage transistor with an extended drain structure 有权
    制造具有延长漏极结构的高压晶体管的方法

    公开(公告)号:US07745291B2

    公开(公告)日:2010-06-29

    申请号:US11807531

    申请日:2007-05-29

    申请人: Donald Ray Disney

    发明人: Donald Ray Disney

    IPC分类号: H01L21/331 H01L21/8222

    摘要: A method for fabricating a high-voltage transistor with an extended drain region includes forming in a semiconductor substrate of a first conductivity type, first and second trenches that define a mesa having respective first and second sidewalls partially filling each of the trenches with a dielectric material that covers the first and second sidewalls. The remaining portions of the trenches are then filled with a conductive material to form first and second field plates. Source and body regions are formed in an upper portion of the mesa, with the body region separating the source from a lower portion of the mesa. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).

    摘要翻译: 一种用于制造具有延伸漏极区域的高压晶体管的方法包括在第一导电类型的半导体衬底中形成第一和第二沟槽,所述第一和第二沟槽限定具有相互的第一和第二侧壁的台面,所述第一和第二侧壁部分地用电介质材料填充每个沟槽 其覆盖第一和第二侧壁。 然后用导电材料填充沟槽的剩余部分以形成第一和第二场板。 源区和体区形成在台面的上部,体区将源与台面的下部分开。 要强调的是,该摘要被提供以符合要求抽象的规则,允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是,它不会用于解释或限制权利要求的范围或含义。 37 CFR 1.72(b)。

    Method of fabricating a high-voltage transistor with an extended drain structure
    85.
    发明申请
    Method of fabricating a high-voltage transistor with an extended drain structure 有权
    制造具有延长漏极结构的高压晶体管的方法

    公开(公告)号:US20090233407A1

    公开(公告)日:2009-09-17

    申请号:US12386392

    申请日:2009-04-18

    申请人: Donald Ray Disney

    发明人: Donald Ray Disney

    IPC分类号: H01L21/336

    摘要: A method for fabricating a high-voltage transistor with an extended drain region includes forming in a semiconductor substrate of a first conductivity type, first and second trenches that define a mesa having respective first and second sidewalls; then partially filling each of the trenches with a dielectric material that covers the first and second sidewalls. The remaining portions of the trenches are then filled with a conductive material to form first and second field plates. Source and body regions are formed in an upper portion of the mesa, with the body region separating the source from a lower portion of the mesa. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

    摘要翻译: 一种用于制造具有延伸漏极区的高电压晶体管的方法包括在第一导电类型的半导体衬底中形成限定具有相应的第一和第二侧壁的台面的第一和第二沟槽; 然后用覆盖第一和第二侧壁的电介质材料部分地填充每个沟槽。 然后用导电材料填充沟槽的剩余部分以形成第一和第二场板。 源区和体区形成在台面的上部,体区将源与台面的下部分开。 要强调的是,该摘要被提供以符合要求抽象的规则,允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是,它不会用于解释或限制权利要求的范围或含义。

    Lateral Trench MOSFET with Conformal Depletion-Assist Layer
    86.
    发明申请
    Lateral Trench MOSFET with Conformal Depletion-Assist Layer 审中-公开
    具有保形消耗辅助层的侧向沟槽MOSFET

    公开(公告)号:US20090206397A1

    公开(公告)日:2009-08-20

    申请号:US12032289

    申请日:2008-02-15

    申请人: Donald Ray Disney

    发明人: Donald Ray Disney

    IPC分类号: H01L29/78

    摘要: A lateral trench DMOS device formed in a substrate of a first conductivity type includes a vertical trench lined with a dielectric layer and containing a gate electrode. A source region of a second conductivity is adjacent the surface of the substrate and a sidewall of the trench. A drain region of the second conductivity type is adjacent the surface of the substrate and spaced apart from the source region. A field oxide region is disposed at the surface of the substrate between the source region and the drain region and a drift region of the second conductivity type extends laterally from the trench sidewall to the drain region. A body region of a first conductivity type is disposed between the source region and the drift region, the body region adjacent the trench sidewall where the body region has a profile that is conformal to the field oxide region.

    摘要翻译: 形成在第一导电类型的衬底中的横向沟槽DMOS器件包括衬有介电层并且包含栅电极的垂直沟槽。 第二导电性的源极区域与衬底的表面和沟槽的侧壁相邻。 第二导电类型的漏极区域与衬底的表面相邻并且与源极区域分开。 场源氧化物区域设置在源极区域和漏极区域之间的衬底的表面处,并且第二导电类型的漂移区域从沟槽侧壁向漏极区域横向延伸。 第一导电类型的主体区域设置在源极区域和漂移区域之间,邻近沟槽侧壁的主体区域,其中主体区域具有与场氧化物区域共形的轮廓。

    Gate etch process for a high-voltage FET

    公开(公告)号:US20080085603A1

    公开(公告)日:2008-04-10

    申请号:US11542083

    申请日:2006-10-03

    申请人: Donald Ray Disney

    发明人: Donald Ray Disney

    IPC分类号: H01L21/302

    摘要: A method, in one embodiment, includes etching first and second dielectric regions in a substantially isotropic manner through first and second openings of a mask layer to create first and second trenches. The first and second dielectric regions are disposed on opposite sides of a mesa of semiconductor material, the mesa having first and second sidewalls that respectively adjoin the first and second dielectric regions. The first and second dielectric regions in the first and second trenches are then etched in a substantially isotropic manner to expose the first and second sidewalls. A gate oxide is formed on the first and second sidewalls of the mesa. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.

    High-voltage lateral transistor with a multi-layered extended drain structure
    88.
    发明授权
    High-voltage lateral transistor with a multi-layered extended drain structure 失效
    具有多层延伸漏极结构的高压横向晶体管

    公开(公告)号:US06987299B2

    公开(公告)日:2006-01-17

    申请号:US10868984

    申请日:2004-06-16

    摘要: A high-voltage transistor with a low specific on-state resistance and that supports high voltage in the off-state includes one or more source regions disposed adjacent to a multi-layered extended drain structure which comprises extended drift regions separated from field plate members by one or more dielectric layers. The layered structure may be fabricated in a variety of orientations. A MOSFET structure may be incorporated into the device adjacent to the source region, or, alternatively, the MOSFET structure may be omitted to produce a high-voltage transistor structure having a stand-alone drift region. It is emphaized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims 37 CFR 1.72(b).

    摘要翻译: 具有低特定导通电阻并且支持处于截止状态的高电压的高电压晶体管包括邻近多层延伸漏极结构设置的一个或多个源极区域,该多个区域延伸漏极结构包括通过 一个或多个电介质层。 层状结构可以以各种取向制造。 可以将MOSFET结构并入到与源极区域相邻的器件中,或者,可以省略MOSFET结构以产生具有独立漂移区域的高压晶体管结构。 重点是提供这个摘要是为了遵守规定抽象的规则,允许搜索者或其他读者快速确定技术公开内容的主题。 提交的理由是,它不会用于解释或限制权利要求的范围或含义37 CFR 1.72(b)。

    High-voltage vertical transistor with a multi-layered extended drain structure
    89.
    发明授权
    High-voltage vertical transistor with a multi-layered extended drain structure 失效
    具有多层延伸漏极结构的高压立式晶体管

    公开(公告)号:US06781198B2

    公开(公告)日:2004-08-24

    申请号:US10158637

    申请日:2002-05-30

    申请人: Donald Ray Disney

    发明人: Donald Ray Disney

    IPC分类号: H01L2976

    摘要: A high-voltage transistor with a low specific on-state resistance and that supports high voltage in the off-state includes one or more source regions disposed adjacent to a multi-layered extended drain structure which comprises extended drift regions separated from field plate members by one or more dielectric layers. With the field plate members at the lowest circuit potential, the transistor supports high voltages applied to the drain in the off-state. The layered structure may be fabricated in a variety of orientations. A MOSFET structure may be incorporated into the device adjacent to the source region, or, alternatively, the MOSFET structure may be omitted to produce a high-voltage transistor structure having a stand-alone drift region.

    摘要翻译: 具有低特定导通电阻并且支持处于截止状态的高电压的高压晶体管包括邻近多层延伸漏极结构设置的一个或多个源极区域,其包括通过 一个或多个电介质层。 在场板成员处于最低电路电位的情况下,晶体管支持在截止状态下施加到漏极的高电压。 层状结构可以以各种取向制造。 可以将MOSFET结构并入到与源极区域相邻的器件中,或者,可以省略MOSFET结构以产生具有独立漂移区域的高压晶体管结构。

    High-voltage transistor with JFET conduction channels
    90.
    发明授权
    High-voltage transistor with JFET conduction channels 失效
    具有JFET导通通道的高压晶体管

    公开(公告)号:US06768171B2

    公开(公告)日:2004-07-27

    申请号:US10137762

    申请日:2002-05-02

    申请人: Donald Ray Disney

    发明人: Donald Ray Disney

    IPC分类号: H01L2976

    摘要: A high voltage insulated gate field-effect transistor with multiple JFET conduction channels comprises a first buried layer disposed in a first epitaxial layer formed on a substrate, a second buried layer disposed in a second epitaxial layer formed on the first epitaxial layer, with the first and second buried layers being spaced vertically apart in a substantially parallel configuration such that a JFET conduction channel of the first conductivity type is formed between the first and second buried layers. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).

    摘要翻译: 具有多个JFET导电沟道的高电压绝缘栅场效应晶体管包括设置在形成于衬底上的第一外延层中的第一掩埋层,设置在形成于第一外延层上的第二外延层中的第二掩埋层, 并且第二掩埋层以基本上平行的构造垂直间隔开,使得在第一和第二掩埋层之间形成第一导电类型的JFET导电沟道。 要强调的是,该摘要被提供以符合要求抽象的规则,允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是,它不会用于解释或限制权利要求的范围或含义。 37 CFR 1.72(b)。