公开(公告)号：US20060151787A1

公开(公告)日：2006-07-13

申请号：US10905595

申请日：2005-01-12

申请人： Huajie Chen ,  Anda Mocuta ,  Stephen Bedell ,  Effendi Leobandung ,  Devendra Sadana

发明人： Huajie Chen ,  Anda Mocuta ,  Stephen Bedell ,  Effendi Leobandung ,  Devendra Sadana

IPC分类号： H01L29/12 ,  H01L21/20

CPC分类号： H01L29/1054 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/0251 ,  H01L21/02532

摘要： A method and structure for fabricating a strained semiconductor on a relaxed SiGe substrate which has dopant diffusion control and defect reduction are provided. Specifically, the dopant diffusion control and defect reduction is achieved in the present invention by providing a SiGe buffer layer between the strained semiconductor and the underlying relaxed SiGe substrate. In accordance with the present invention, the SiGe buffer layer has a Ge content that is less than the Ge content which is present in the relaxed SiGe substrate.

摘要翻译： 提供了在具有掺杂剂扩散控制和缺陷减少的松弛SiGe衬底上制造应变半导体的方法和结构。 具体地，通过在应变半导体和下面的弛豫SiGe衬底之间提供SiGe缓冲层，在本发明中实现了掺杂剂扩散控制和缺陷减少。 根据本发明，SiGe缓冲层的Ge含量小于弛豫SiGe衬底中存在的Ge含量。

公开(公告)号：US06437400B1

公开(公告)日：2002-08-20

申请号：US09837136

申请日：2001-04-18

申请人： Effendi Leobandung

发明人： Effendi Leobandung

IPC分类号： H01L2976

摘要： A process for fabricating a tapered trench on a silicon substrate. The process comprises the steps of forming an initial trench in the substrate and implanting nitrogen ions on the initial trench side walls. More nitrogen ions are implanted adjacent the exposed surface of the substrate than adjacent the trench bottom. Finally, the initial trench side walls are oxidized to create the tapered shape.

公开(公告)号：US06404014B1

公开(公告)日：2002-06-11

申请号：US09708337

申请日：2000-11-08

申请人： Effendi Leobandung ,  Devendra K. Sadana ,  Dominic J. Schepis ,  Ghavam Shahidi

发明人： Effendi Leobandung ,  Devendra K. Sadana ,  Dominic J. Schepis ,  Ghavam Shahidi

IPC分类号： H01L2701

CPC分类号： H01L21/76264 ,  H01L21/762 ,  H01L21/76278

摘要： A planar silicon-on-insulator (SOI) structure and a process for fabricating the structure. The SOI structure has a silicon wafer, an oxide layer, and a silicon layer. Trenches are formed, extending from the top surface of the structure to the silicon wafer, and are filled with a semiconductor. The trenches have a top, a bottom, and side walls. The side walls have side-wall silicon portions. The side-wall silicon portions of the trench side walls are covered by trench side-wall oxide layers. A protective side wall extends over the trench side walls and trench side-wall oxide layers from the trench top to the trench bottom.

摘要翻译： 一种平面绝缘体上硅（SOI）结构及其制造方法。 SOI结构具有硅晶片，氧化物层和硅层。 形成从结构的顶表面延伸到硅晶片并且填充有半导体的沟槽。 沟槽有顶部，底部和侧壁。 侧壁具有侧壁硅部分。 沟槽侧壁的侧壁硅部分被沟槽侧壁氧化物层覆盖。 保护侧壁从沟槽顶部到沟槽底部在沟槽侧壁和沟槽侧壁氧化物层上延伸。

公开(公告)号：US06339005B1

公开(公告)日：2002-01-15

申请号：US09425394

申请日：1999-10-22

申请人： Andres Bryant ,  Jerome B. Lasky ,  Effendi Leobandung ,  Dominic J. Schepis

发明人： Andres Bryant ,  Jerome B. Lasky ,  Effendi Leobandung ,  Dominic J. Schepis

IPC分类号： H01L21336

CPC分类号： H01L29/66643 ,  H01L29/458 ,  H01L29/6653 ,  H01L29/66659 ,  H01L29/66772 ,  H01L29/7839 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78621 ,  H01L29/78624 ,  H01L29/812

摘要： A silicon on insulator transistor is disclosed which has a Schottky contact to the body. The Schottky contact may be formed on the source and/or drain side of the gate conductor. A spacer, with at least a part thereof being disposable, is formed on the sidewalls of the gate conductor. Extension regions are provided in the substrate which extend under the spacer and the gate conductor. Source and drain diffusion regions are implanted into the substrate adjacent to the extension regions. The disposable part of the spacer is then removed to expose a portion of the extension region. A metal layer is formed at least in the extension regions, resulting in the Schottky contact.

摘要翻译： 公开了一种绝缘体上硅晶体管，其具有与身体的肖特基接触。 肖特基接触可以形成在栅极导体的源极和/或漏极侧。 在栅极导体的侧壁上形成有至少一部分是一次性的间隔物。 延伸区域设置在衬底下延伸在间隔物和栅极导体之下。 源极和漏极扩散区域被注入邻近延伸区域的衬底中。 然后移除间隔件的一次性部分以暴露延伸区域的一部分。 至少在延伸区域中形成金属层，导致肖特基接触。

公开(公告)号：US6069380A

公开(公告)日：2000-05-30

申请号：US900947

申请日：1997-07-25

申请人： Stephen Y. Chou ,  Lingjie Guo ,  Effendi Leobandung

发明人： Stephen Y. Chou ,  Lingjie Guo ,  Effendi Leobandung

IPC分类号： H01L29/788

CPC分类号： B82Y10/00 ,  H01L29/7888 ,  Y10S977/937

摘要： A Single Electron MOS Memory (SEMM), in which one bit of information is represented by storing only one electron, has been demonstrated at room temperature. The SEMM is a floating gate Metal-Oxide-Semiconductor (MOS) transistor in silicon with a channel width (about 10 nanometers) which is smaller than the Debye screening length of a single electron stored on the floating gate, and a nanoscale polysilicon dot (about 7 nanometers by 7 nanometers by 2 nanometers) as the floating gate which is positioned between the channel and the control gate. An electron stored on the floating gate can screen the entire channel from the potential on the control gate, and lead to: (i) a discrete shift in the threshold voltage; (ii) a staircase relation between the charging voltage and the shift; and (iii) a self-limiting charging process. The structure and fabrication of the SEMM is well adapted to the manufacture of ultra large-scale integrated circuits.

摘要翻译： 已经在室温下证明了单电子MOS存储器（SEMM），其中一位信息仅通过仅存储一个电子来表示。 SEMM是硅中的浮栅金属氧化物半导体（MOS）晶体管，其通道宽度（约10纳米）小于存储在浮置栅极上的单个电子的德拜屏蔽长度，以及纳米级多晶硅点（ 约7纳米×7纳米×2纳米）作为位于通道和控制门之间的浮动栅极。 存储在浮置栅极上的电子可以从控制栅极上的电位屏蔽整个通道，并导致：（i）阈值电压的离散移位; （ii）充电电压与偏移之间的阶梯关系; 和（iii）自限制充电过程。 SEMM的结构和制造适应于超大规模集成电路的制造。