公开(公告)号：US20060151787A1

公开(公告)日：2006-07-13

申请号：US10905595

申请日：2005-01-12

申请人： Huajie Chen ,  Anda Mocuta ,  Stephen Bedell ,  Effendi Leobandung ,  Devendra Sadana

发明人： Huajie Chen ,  Anda Mocuta ,  Stephen Bedell ,  Effendi Leobandung ,  Devendra Sadana

IPC分类号： H01L29/12 ,  H01L21/20

CPC分类号： H01L29/1054 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/0251 ,  H01L21/02532

摘要： A method and structure for fabricating a strained semiconductor on a relaxed SiGe substrate which has dopant diffusion control and defect reduction are provided. Specifically, the dopant diffusion control and defect reduction is achieved in the present invention by providing a SiGe buffer layer between the strained semiconductor and the underlying relaxed SiGe substrate. In accordance with the present invention, the SiGe buffer layer has a Ge content that is less than the Ge content which is present in the relaxed SiGe substrate.

摘要翻译： 提供了在具有掺杂剂扩散控制和缺陷减少的松弛SiGe衬底上制造应变半导体的方法和结构。 具体地，通过在应变半导体和下面的弛豫SiGe衬底之间提供SiGe缓冲层，在本发明中实现了掺杂剂扩散控制和缺陷减少。 根据本发明，SiGe缓冲层的Ge含量小于弛豫SiGe衬底中存在的Ge含量。

公开(公告)号：US20050242340A1

公开(公告)日：2005-11-03

申请号：US11062993

申请日：2005-02-22

申请人： Dureseti Chidambarrao ,  Effendi Leobandung ,  Anda Mocuta ,  Haining Yang ,  Huilong Zhu

发明人： Dureseti Chidambarrao ,  Effendi Leobandung ,  Anda Mocuta ,  Haining Yang ,  Huilong Zhu

IPC分类号： C30B25/18 ,  C30B29/06 ,  H01L21/20 ,  H01L21/285 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L29/786 ,  H01L29/06 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072

CPC分类号： H01L29/78696 ,  C30B25/18 ,  C30B29/06 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/28562 ,  H01L29/1054 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7834 ,  H01L29/78687

摘要： A planar NFET on a strained silicon layer supported by a SiGe layer achieves reduced external resistance by removing SiGe material outside the transistor body and below the strained silicon layer and replacing the removed material with epitaxial silicon, thereby providing lower resistance for the transistor electrodes and permitting better control over Arsenic diffusion.

公开(公告)号：US20070252203A1

公开(公告)日：2007-11-01

申请号：US11774221

申请日：2007-07-06

申请人： Huilong Zhu ,  Effendi Leobandung ,  Anda Mocuta ,  Dan Mocuta

发明人： Huilong Zhu ,  Effendi Leobandung ,  Anda Mocuta ,  Dan Mocuta

IPC分类号： H01L29/78

CPC分类号： H01L29/7842 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/105 ,  H01L29/1608 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： The present invention comprises a method for forming a semiconducting device including the steps of providing a layered structure including a substrate, a low diffusivity layer of a first-conductivity dopant; and a channel layer; forming a gate stack atop a protected surface of the channel layer; etching the layered structure selective to the gate stack to expose a surface of the substrate, where a remaining portion of the low diffusivity layer provides a retrograded island substantially aligned to the gate stack having a first dopant concentration to reduce short-channel effects without increasing leakage; growing a Si-containing material atop the recessed surface of the substrate; and doping the Si-containing material with a second-conductivity dopant at a second dopant concentration. The low diffisivity layer may be Si1-x-yGexZy, where Z can be carbon (C), xenon (Xe), germanium (Ge), krypton (Kr), argon (Ar), nitrogen (N), or combinations thereof.

摘要翻译： 本发明包括一种形成半导体器件的方法，包括以下步骤：提供包括衬底，第一导电掺杂剂的低扩散层的分层结构; 和通道层; 在沟道层的受保护表面上方形成栅极堆叠; 蚀刻对栅极堆叠选择性的层状结构以暴露衬底的表面，其中低扩散层的剩余部分提供基本上与具有第一掺杂剂浓度的栅极堆叠对准的退化岛，以减少短沟道效应而不增加泄漏 ; 在衬底的凹陷表面的顶部生长含Si材料; 并且以第二掺杂剂浓度用第二导电掺杂剂掺杂含Si材料。 低扩散层可以是Si 1-xy X z Z z，其中Z可以是碳（C），氙（Xe）， 锗（Ge），氪（Kr），氩（Ar），氮（N）或其组合。

公开(公告)号：US20060068555A1

公开(公告)日：2006-03-30

申请号：US10954838

申请日：2004-09-30

申请人： Huilong Zhu ,  Effendi Leobandung ,  Anda Mocuta ,  Dan Mocuta

发明人： Huilong Zhu ,  Effendi Leobandung ,  Anda Mocuta ,  Dan Mocuta

IPC分类号： H01L21/336

CPC分类号： H01L29/7842 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/105 ,  H01L29/1608 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： The present invention comprises a method for forming a semiconducting device including the steps of providing a layered structure including a substrate, a low diffusivity layer of a first-conductivity dopant; and a channel layer; forming a gate stack atop a protected surface of the channel layer; etching the layered structure selective to the gate stack to expose a surface of the substrate, where a remaining portion of the low diffusivity layer provides a retrograded island substantially aligned to the gate stack having a first dopant concentration to reduce short-channel effects without increasing leakage; growing a Si-containing material atop the recessed surface of the substrate; and doping the Si-containing material with a second-conductivity dopant at a second dopant concentration. The low diffusivity layer may be Si1-x-yGexZy, where Z can be carbon (C), xenon (Xe), germanium (Ge), krypton (Kr), argon (Ar), nitrogen (N), or combinations thereof.

摘要翻译： 本发明包括一种形成半导体器件的方法，包括以下步骤：提供包括衬底，第一导电掺杂剂的低扩散层的分层结构; 和通道层; 在沟道层的受保护表面上方形成栅极堆叠; 蚀刻对栅极堆叠选择性的层状结构以暴露衬底的表面，其中低扩散层的剩余部分提供基本上与具有第一掺杂剂浓度的栅极堆叠对准的退化岛，以减少短沟道效应而不增加泄漏 ; 在衬底的凹陷表面的顶部生长含Si材料; 并且以第二掺杂剂浓度用第二导电掺杂剂掺杂含Si材料。 低扩散性层可以是Si 1-xy X z Z z，其中Z可以是碳（C），氙（Xe）， 锗（Ge），氪（Kr），氩（Ar），氮（N）或其组合。

公开(公告)号：US20060063358A1

公开(公告)日：2006-03-23

申请号：US10943354

申请日：2004-09-17

申请人： Stephen Bedell ,  Anda Mocuta

发明人： Stephen Bedell ,  Anda Mocuta

IPC分类号： H01L21/20 ,  H01L21/31

CPC分类号： H01L21/32105 ,  H01L21/84 ,  Y10S438/967

摘要： A method of forming a substantially relaxed SiGe-on-insulator substrate in which the consumption of the sidewalls of SiGe-containing island structures during a high temperature relaxation annealing is substantially prevented or eliminated is provided. The method serves to maintain the original lateral dimensions of the patterned SiGe-containing islands, while providing a uniform and homogeneous Ge fraction of the islands that is independent of each island size. The method includes forming an oxidation mask on at least sidewalls of a SiGe-containing island structure that is located on a barrier layer that is resistant to Ge diffusion. A heating step is then employed to cause at least relaxation within the SiGe-containing island structure. The presence of the oxidation mask substantially prevents consumption of at least the sidewalls of the SiGe-containing island structure during the heating step.

公开(公告)号：US20050145941A1

公开(公告)日：2005-07-07

申请号：US10751916

申请日：2004-01-07

申请人： Stephen Bedell ,  Kevin Chan ,  Dureseti Chidambarrao ,  Silke Christiansen ,  Jack Chu ,  Anthony Domenicucci ,  Kam-Leung Lee ,  Anda Mocuta ,  John Ott ,  Qiqing Ouyang

发明人： Stephen Bedell ,  Kevin Chan ,  Dureseti Chidambarrao ,  Silke Christiansen ,  Jack Chu ,  Anthony Domenicucci ,  Kam-Leung Lee ,  Anda Mocuta ,  John Ott ,  Qiqing Ouyang

IPC分类号： H01L21/336 ,  H01L21/84 ,  H01L27/01 ,  H01L27/12 ,  H01L29/786

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

摘要： A strained Fin Field Effect Transistor (FinFET) (and method for forming the same) includes a relaxed first material having a sidewall, and a strained second material formed on the sidewall of the first material. The relaxed first material and the strained second material form a fin of the FinFET.

摘要翻译： 应变的Fin场效应晶体管（FinFET）（及其形成方法）包括具有侧壁的松弛的第一材料和形成在第一材料的侧壁上的应变的第二材料。 松弛的第一材料和应变的第二材料形成FinFET的鳍。

公开(公告)号：US20060220112A1

公开(公告)日：2006-10-05

申请号：US10907464

申请日：2005-04-01

申请人： Huilong Zhu ,  Kam-Leung Lee ,  Jinghong Li ,  Anda Mocuta

发明人： Huilong Zhu ,  Kam-Leung Lee ,  Jinghong Li ,  Anda Mocuta

IPC分类号： H01L29/76

CPC分类号： H01L21/26513 ,  H01L21/26506 ,  H01L29/1054

摘要： Methods and structure formed for retarding diffusion of a dopant into a channel of a strained Si—SiGe CMOS device are disclosed. The methods form a diffusion retardant region in a substrate including at least one diffusion retardant species such as xenon (Xe), and then form a channel layer over the diffusion retardant region. Each step is conducted prior to formation of a gate on the substrate. As a result, if necessary, the diffusion retardant region can be annealed and cleaned or etched to remove defects in the substrate to reduce external resistance and leakage of devices. The diffusion retardant region positioned under the channel slows down the diffusion of a dopant, e.g., arsenic (As). The invention is also applicable to other substrates.

摘要翻译： 公开了用于将掺杂剂扩散到应变Si-SiGe CMOS器件的沟道中的方法和结构。 该方法在包括至少一种扩散阻挡物质如氙（Xe）的基板中形成扩散阻挡区，然后在扩散阻挡区上形成通道层。 每个步骤在基板上形成栅极之前进行。 结果，如果需要，可以对扩散阻挡区域进行退火和清洁或蚀刻以去除衬底中的缺陷，以减少器件的外部电阻和漏电。 位于通道下方的扩散阻滞区减慢了掺杂剂（例如砷）（As）的扩散。 本发明也适用于其它基材。

公开(公告)号：US20060189061A1

公开(公告)日：2006-08-24

申请号：US11407313

申请日：2006-04-19

申请人： Ricky Amos ,  Diane Boyd ,  Cyril Cabral ,  Richard Kaplan ,  Jakub Kedzierski ,  Victor Ku ,  Woo-Hyeong Lee ,  Ying Li ,  Anda Mocuta ,  Vijay Narayanan ,  An Steegen ,  Maheswaren Surendra

发明人： Ricky Amos ,  Diane Boyd ,  Cyril Cabral ,  Richard Kaplan ,  Jakub Kedzierski ,  Victor Ku ,  Woo-Hyeong Lee ,  Ying Li ,  Anda Mocuta ,  Vijay Narayanan ,  An Steegen ,  Maheswaren Surendra

IPC分类号： H01L21/8238

CPC分类号： H01L21/76897 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/823835 ,  H01L29/66545 ,  H01L29/6656

摘要： The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.

摘要翻译： 本发明提供了一种互补金属氧化物半导体集成工艺，其中在栅极电介质顶部制造多个硅化金属栅极。 使用本发明的集成方案形成的每个硅化金属栅极与硅化物金属栅极的尺寸无关，具有相同的硅化物金属相和基本上相同的高度。 本发明还提供了形成具有硅化物触点的CMOS结构的各种方法，其中多晶硅栅极高度在半导体结构的整个表面上基本相同。

公开(公告)号：US20050186747A1

公开(公告)日：2005-08-25

申请号：US10786901

申请日：2004-02-25

申请人： Ricky Amos ,  Diane Boyd ,  Cyril Cabral ,  Richard Kaplan ,  Jakub Kedzierski ,  Victor Ku ,  Woo-Hyeong Lee ,  Ying Li ,  Anda Mocuta ,  Vijay Narayanan ,  An Steegen ,  Maheswaran Surendra

发明人： Ricky Amos ,  Diane Boyd ,  Cyril Cabral ,  Richard Kaplan ,  Jakub Kedzierski ,  Victor Ku ,  Woo-Hyeong Lee ,  Ying Li ,  Anda Mocuta ,  Vijay Narayanan ,  An Steegen ,  Maheswaran Surendra

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/339 ,  H01L21/60 ,  H01L21/8238

CPC分类号： H01L21/76897 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/823835 ,  H01L29/66545 ,  H01L29/6656

摘要： The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.

摘要翻译： 本发明提供了一种互补金属氧化物半导体集成工艺，其中在栅极电介质顶部制造多个硅化金属栅极。 使用本发明的集成方案形成的每个硅化金属栅极与硅化物金属栅极的尺寸无关，具有相同的硅化物金属相和基本上相同的高度。 本发明还提供了形成具有硅化物触点的CMOS结构的各种方法，其中多晶硅栅极高度在半导体结构的整个表面上基本相同。

公开(公告)号：US20080108186A1

公开(公告)日：2008-05-08

申请号：US12002807

申请日：2007-12-19

申请人： Terence Hook ,  Anda Mocuta ,  Jeffrey Sleight ,  Anthony Stamper

发明人： Terence Hook ,  Anda Mocuta ,  Jeffrey Sleight ,  Anthony Stamper

IPC分类号： H01L21/84

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0251 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/1207

摘要： In a method of fabricating a CMOS structure, a bulk device can be formed in a first region in conductive communication with an underlying bulk region of the substrate. A first gate conductor may overlie the first region. An SOI device can be formed which has a source drain conduction path in a SOI layer, i.e., a semiconductor layer that is separated from the bulk region by a buried dielectric region. The crystal orientations of the SOI layer and the bulk region can be different. A first diode can be formed in a second region of the substrate in conductive communication with the bulk region. The first diode may be connected in a reverse-biased orientation to a first gate conductor above the SOI layer, such that a voltage on the gate conductor that exceeds the breakdown voltage can be discharged through the first diode to the bulk region of the substrate. A second diode may be formed in a third region of the substrate in conductive communication with the bulk region. The second diode may be connected in a reverse-biased orientation to a source region or a drain region of an NFET.

摘要翻译： 在制造CMOS结构的方法中，本体器件可以形成在与衬底的下面的主体区域导电连通的第一区域中。 第一栅极导体可以覆盖在第一区域上。 可以形成在SOI层中具有源极漏极传导路径的SOI器件，即通过掩埋电介质区域与本体区域分离的半导体层。 SOI层和体区的晶体取向可以不同。 第一二极管可以形成在衬底的与体区导电连通的第二区域中。 第一二极管可以以反向偏置的方式连接到SOI层上方的第一栅极导体，使得超过击穿电压的栅极导体上的电压可以通过第一二极管放电到衬底的主体区域。 第二二极管可以形成在衬底的与体区导电连通的第三区域中。 第二二极管可以以反向偏置的方式连接到NFET的源极区域或漏极区域。