公开(公告)号：US20070045775A1

公开(公告)日：2007-03-01

申请号：US11212187

申请日：2005-08-26

申请人： Thomas Adam ,  Dureseti Chidambarrao

发明人： Thomas Adam ,  Dureseti Chidambarrao

IPC分类号： H01L29/00

CPC分类号： H01L29/7378 ,  H01L29/161 ,  H01L29/165

摘要： The present invention relates to a high performance heterojunction bipolar transistor (HBT) having a base region with a SiGe-containing layer therein. The SiGe-containing layer is not more than about 100 nm thick and has a predetermined critical germanium content. The SiGe-containing layer further has an average germanium content of not less than about 80% of the predetermined critical germanium content. The present invention also relates to a method for enhancing carrier mobility in a HBT having a SiGe-containing base layer, by uniformly increasing germanium content in the base layer so that the average germanium content therein is not less than 80% of a critical germanium content, which is calculated based on the thickness of the base layer, provided that the base layer is not more than 100 nm thick.

摘要翻译： 本发明涉及在其中具有含SiGe的层的基极区域的高性能异质结双极晶体管（HBT）。 含SiGe的层的厚度不超过约100nm，具有预定的临界锗含量。 含SiGe的层还具有不小于预定临界锗含量的约80％的平均锗含量。 本发明还涉及通过均匀地提高基底层中的锗含量，使其中的平均锗含量不低于临界锗含量的80％，来提高具有含SiGe的基底层的HBT中的载流子迁移率的方法 ，其基于基底层的厚度计算，条件是基底层不大于100nm厚。

公开(公告)号：US20060273841A1

公开(公告)日：2006-12-07

申请号：US11160056

申请日：2005-06-07

申请人： David Hanson ,  Dureseti Chidambarrao ,  Gregory Fredeman ,  David Onsongo

发明人： David Hanson ,  Dureseti Chidambarrao ,  Gregory Fredeman ,  David Onsongo

IPC分类号： H01H37/76

CPC分类号： G11C17/18

摘要： A circuit is provided which is operable to program an electrically alterable element, e.g., fuse or antifuse, to a programmed state and determine whether the electrically alterable element is in the programmed state or not. Such circuit includes a multiple conduction state field effect transistor (“multi-state FET”) having at least one of a source or a drain coupled to the electrically alterable element to apply a current to the electrically alterable element. The multi-state FET has a first threshold voltage and a second threshold voltage, both being effective at the same time, the second threshold voltage being higher than the first threshold voltage. The gate is operable to control operation of the multi-state FET in multiple states including a) an essentially nonconductive state; b) a first or “low” conductive state when a gate-source voltage exceeds the first threshold voltage, in which the multi-state FET is biased to conduct a relatively low magnitude current for determining the state of the fuse; and c) a second conductive state when the gate-source voltage exceeds the second threshold voltage, in which the multi-state FET is biased to conduct a relatively high magnitude programming current.

摘要翻译： 提供了一种电路，其可操作以将电可更改元件（例如，熔丝或反熔丝）编程到编程状态，并确定电可更改元件是否处于编程状态。 这种电路包括多导通状态场效应晶体管（“多状态FET”），其具有耦合到可电可变元件的源极或漏极中的至少一个，以将电流施加到电可更改元件。 多状态FET具有第一阈值电压和第二阈值电压，两者均同时有效，第二阈值电压高于第一阈值电压。 栅极可操作以控制多状态FET的操作，包括a）基本上非导通状态; b）当栅极 - 源极电压超过第一阈值电压时，第一或“低”导通状态，其中多态FET被偏置以传导相对低的幅度电流以确定保险丝的状态; 以及c）当所述栅极 - 源极电压超过所述第二阈值电压时，所述第二导电状态是所述多态FET被偏置以导通相对高的编程电流。

公开(公告)号：US07102914B2

公开(公告)日：2006-09-05

申请号：US10708381

申请日：2004-02-27

申请人： Xiangdong Chen ,  Dureseti Chidambarrao ,  Geng Wang

发明人： Xiangdong Chen ,  Dureseti Chidambarrao ,  Geng Wang

IPC分类号： G11C11/24 ,  G11C11/34

CPC分类号： H01L27/10864 ,  H01L27/0214 ,  H01L27/10841

摘要： A novel transistor structure for a DRAM cell includes two deep trenches, one trench including a vertical storage cell for storing the data and the second trench including a vertical control cell for controlling the p-well voltage, which, in effect, places part of the p-well in a floating condition thus decreasing the threshold voltage as compared to when the vertical pass transistor is in an off-state. This enables the transistor to exhibit increased gate overdrive and drive current during an active wordline voltage commonly applied to both gates of the storage and control cells.

摘要翻译： 用于DRAM单元的新型晶体管结构包括两个深沟槽，一个沟槽包括用于存储数据的垂直存储单元，第二沟槽包括用于控制p阱电压的垂直控制单元，其实际上将部分 p阱处于浮置状态，从而与垂直传输晶体管处于截止状态时相比降低阈值电压。 这使得晶体管能够在通常施加到存储和控制单元的两个栅极的有效字线电压期间表现出增加的栅极过驱动和驱动电流。

公开(公告)号：US20060145274A1

公开(公告)日：2006-07-06

申请号：US11365502

申请日：2006-03-02

申请人： Dureseti Chidambarrao ,  Omer Dokumaci ,  Oleg Gluschenkov

发明人： Dureseti Chidambarrao ,  Omer Dokumaci ,  Oleg Gluschenkov

IPC分类号： H01L29/94

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823828

摘要： A method for manufacturing an integrated circuit comprising a plurality of semiconductor devices including an n-type field effect transistor and a p-type field effect transistor by covering the p-type field effect transistor with a mask, and oxidizing a portion of a gate polysilicon of the n-type field effect transistor, such that tensile mechanical stresses are formed within a channel of the n-type field effect transistor.

公开(公告)号：US20060124993A1

公开(公告)日：2006-06-15

申请号：US10905041

申请日：2004-12-13

申请人： Huilong Zhu ,  Lawrence Clevenger ,  Omer Dokumaci ,  Kaushik Kumar ,  Carl Radens ,  Dureseti Chidambarrao

发明人： Huilong Zhu ,  Lawrence Clevenger ,  Omer Dokumaci ,  Kaushik Kumar ,  Carl Radens ,  Dureseti Chidambarrao

IPC分类号： H01L29/76

CPC分类号： H01L29/785 ,  H01L29/1083 ,  H01L29/66795

摘要： A novel transistor structure and method for fabricating the same. The transistor structure comprises (a) a substrate and (b) a semiconductor region, a gate dielectric region, and a gate region on the substrate, wherein the gate dielectric region is sandwiched between the semiconductor region and the gate region, wherein the semiconductor region is electrically insulated from the gate region by the gate dielectric region, wherein the semiconductor region comprises a channel region and first and second source/drain regions, wherein the channel region is sandwiched between the first and second source/drain regions, wherein the first and second source/drain regions are aligned with the gate region, wherein the channel region and the gate dielectric region (i) share an interface surface which is essentially perpendicular to a top surface of the substrate, and (ii) do not share any interface surface that is essentially parallel to a top surface of the substrate.

摘要翻译： 一种新颖的晶体管结构及其制造方法。 晶体管结构包括（a）衬底和（b）衬底上的半导体区域，栅极介电区域和栅极区域，其中栅极电介质区域夹在半导体区域和栅极区域之间，其中半导体区域 通过所述栅极电介质区域与所述栅极区域电绝缘，其中所述半导体区域包括沟道区域和第一和第二源极/漏极区域，其中所述沟道区域夹在所述第一和第二源极/漏极区域之间，其中所述第一和/ 第二源极/漏极区域与栅极区域对准，其中沟道区域和栅极电介质区域（i）共享基本上垂直于衬底顶表面的界面，以及（ii）不共享任何界面表面 其基本上平行于衬底的顶表面。

公开(公告)号：US07045873B2

公开(公告)日：2006-05-16

申请号：US10728750

申请日：2003-12-08

申请人： Xiangdong Chen ,  Dureseti Chidambarrao ,  Geng Wang

发明人： Xiangdong Chen ,  Dureseti Chidambarrao ,  Geng Wang

IPC分类号： H01L29/00

CPC分类号： H01L29/783

摘要： Provision of a body control contact adjacent a transistor and between the transistor and a contact to the substrate or well in which the transistor is formed allows connection and disconnection of the substrate of the transistor to and from a zero (ground) or substantially arbitrary low voltage in accordance with control signals applied to the gate of the transistor to cause the transistor to exhibit a variable threshold which maintains good performance at low supply voltages and reduces power consumption/dissipation which is particularly advantageous in portable electronic devices. Floating body effects (when the transistor substrate in disconnected from a voltage source in the “on” state) are avoided since the substrate is discharged when the transistor is switched to the “off” state. The transistor configuration can be employed with both n-type and p-type transistors which may be in complementary pairs.

摘要翻译： 提供与晶体管相邻并且晶体管与形成晶体管的衬底或阱的接触之间的身体控制接触允许晶体管的衬底与零（接地）或基本上任意的低电压的连接和断开 根据施加到晶体管的栅极的控制信号，使晶体管呈现可变阈值，其在低电源电压下保持良好的性能，并降低了在便携式电子设备中特别有利的功耗/耗散。 避免浮体效应（当晶体管基板与电压源处于“导通”状态断开时），因为当晶体管切换到“关闭”状态时，衬底被放电。 晶体管配置可以与可以互补对的n型和p型晶体管一起使用。

公开(公告)号：US20060091442A1

公开(公告)日：2006-05-04

申请号：US11298800

申请日：2005-12-09

申请人： James Adkisson ,  Gary Bronner ,  Dureseti Chidambarrao ,  Ramachandra Divakaruni ,  Carl Radens

发明人： James Adkisson ,  Gary Bronner ,  Dureseti Chidambarrao ,  Ramachandra Divakaruni ,  Carl Radens

IPC分类号： H01L29/94

CPC分类号： H01L27/10841 ,  H01L27/10864 ,  H01L27/10867

摘要： The present invention provides a vertical memory device formed in a silicon-on-insulator substrate, where a bitline contacting the upper surface of the silicon-on-insulator substrate is electrically connected to the vertical memory device through an upper strap diffusion region formed through a buried oxide layer. The upper strap diffusion region is formed by laterally etching a portion of the buried oxide region to produce a divot, in which doped polysilicon is deposited. The upper strap region diffusion region also provides the source for the vertical transistor of the vertical memory device. The vertical memory device may also be integrated with a support region having logic devices formed atop the silicon-on-insulator substrate.

公开(公告)号：US07037770B2

公开(公告)日：2006-05-02

申请号：US10687608

申请日：2003-10-20

申请人： Dureseti Chidambarrao ,  Omer H. Dokumaci

发明人： Dureseti Chidambarrao ,  Omer H. Dokumaci

IPC分类号： H01L21/00

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66621 ,  Y10S438/933

摘要： A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. An SiGe layer is grown in the channel of the nFET channel and a Si:C layer is grown in the pFET channel. The SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component in an overlying grown epitaxial layer. In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel. In a further implementation, the SiGe layer is grown in both the nFET and pFET channels. In this implementation, the stress level in the pFET channel should be greater than approximately 3 GPa.

摘要翻译： 半导体器件及半导体器件的制造方法。 半导体器件包括用于pFET和nFET的沟道。 在nFET沟道的沟道中生长SiGe层，并且在pFET沟道中生长Si：C层。 SiGe和Si：C层与下层Si层的晶格网络匹配，以在覆盖的生长的外延层中产生应力分量。 在一个实现中，这导致pFET沟道中的压缩分量和nFET沟道中的拉伸分量。 在另一实施方案中，SiGe层在nFET和pFET沟道中生长。 在这种实现中，pFET通道中的应力水平应该大于3GPa。

公开(公告)号：US20060019458A1

公开(公告)日：2006-01-26

申请号：US10710548

申请日：2004-07-20

申请人： Dureseti Chidambarrao ,  Gregory Freeman ,  Marwan Khater

发明人： Dureseti Chidambarrao ,  Gregory Freeman ,  Marwan Khater

IPC分类号： H01L21/331 ,  H01L21/8222

CPC分类号： H01L29/66242 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7378

摘要： The mobility of charge carriers in a bipolar (BJT) device is increased by creating compressive strain in the device to increase mobility of electrons in the device, and creating tensile strain in the device to increase mobility of holes in the device. The compressive and tensile strain are created by applying a stress film adjacent an emitter structure of the device and atop a base film of the device. In this manner, the compressive and tensile strain are located in close proximity to an intrinsic portion of the device. A suitable material for the stress film is nitride. The emitter structure may be “T-shaped”, having a lateral portion atop an upright portion, a bottom of the upright portion forms a contact to the base film, and the lateral portion overhangs the base film.

摘要翻译： 双极（BJT）器件中的载流子的迁移率通过在器件中产生压缩应变以增加器件中电子的迁移率而增加，并且在器件中产生拉伸应变以增加器件中的孔的移动性。 通过在装置的发射极结构附近施加应力膜并且在器件的基底上方施加应力膜来产生压缩和拉伸应变。 以这种方式，压缩和拉伸应变位于设备本身部分附近。 适用于应力膜的材料是氮化物。 发射体结构可以是“T形”，其具有在直立部分顶部的侧面部分，直立部分的底部形成与基底膜的接触，并且侧向部分悬垂在基底膜上。

公开(公告)号：US20050269561A1

公开(公告)日：2005-12-08

申请号：US10859736

申请日：2004-06-03

申请人： Dureseti Chidambarrao ,  Omer Dokumaci ,  Oleg Gluschenkov ,  Huilong Zhu

发明人： Dureseti Chidambarrao ,  Omer Dokumaci ,  Oleg Gluschenkov ,  Huilong Zhu

IPC分类号： H01L21/00 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/78 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054

摘要： The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate, a first layered stack atop the substrate, the first layered stack comprising a first Si-containing portion of the substrate, a compressive layer atop the Si-containing portion of the substrate, and a semiconducting silicon layer atop the compressive layer; and a second layered stack atop the substrate, the second layered stack comprising a second-silicon containing layer portion of the substrate, a tensile layer atop the second Si-containing portion of the substrate, and a second semiconducting silicon-layer atop the tensile layer.

摘要翻译： 本发明提供一种应变Si结构，其中该结构的nFET区域被拉紧并且该结构的pFET区域被压缩而变形。 广义上，应变Si结构包括衬底，在衬底顶部的第一层叠堆叠，第一层叠堆叠包括衬底的第一含Si部分，衬底的含Si部分顶部的压缩层和半导体硅 层在压缩层顶上; 以及在所述衬底顶部的第二层叠叠层，所述第二层叠堆叠包括所述衬底的第二硅含有层部分，在所述衬底的所述第二含Si部分顶部的拉伸层，以及在所述拉伸层顶部的第二半导体硅层 。