公开(公告)号：US08193086B2

公开(公告)日：2012-06-05

申请号：US12640444

申请日：2009-12-17

申请人： Tobias Letz ,  Frank Feustel

发明人： Tobias Letz ,  Frank Feustel

IPC分类号： H01L21/4763

CPC分类号： H01L21/76814 ,  H01L21/76826 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76886

摘要： Electromigration behavior in complex metallization systems of semiconductor devices may be enhanced at critical areas between a metal line and a via by locally forming a copper/silicon compound. In some illustrative embodiments, the formation of the copper/silicon compound may be combined with other treatments for cleaning the exposed surface areas and/or modifying the molecular structure thereof.

摘要翻译： 通过局部形成铜/硅化合物，可以在金属线和通孔之间的关键区域增强半导体器件复杂金属化系统中的电迁移行为。 在一些说明性实施例中，铜/硅化合物的形成可以与用于清洁暴露的表面区域和/或改变其分子结构的其它处理组合。

公开(公告)号：US20100244028A1

公开(公告)日：2010-09-30

申请号：US12749805

申请日：2010-03-30

申请人： Frank Feustel ,  Tobias Letz ,  Frank Koschinsky

发明人： Frank Feustel ,  Tobias Letz ,  Frank Koschinsky

IPC分类号： H01L21/768 ,  H01L23/544

CPC分类号： H01L22/12 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

摘要： During the formation of a complex metallization system, the influence of a manufacturing environment on sensitive barrier/seed material systems may be monitored or controlled by using an appropriate test pattern and applying an appropriate test strategy. For example, actual probe and reference substrates may be prepared and may be processed with and without exposure to the manufacturing environment of interest, thereby enabling an efficient evaluation of one or more parameters of the environment. Furthermore, an “optimized” manufacturing environment may be obtained on the basis of the test strategy disclosed herein.

摘要翻译： 在形成复杂的金属化系统期间，可以通过使用适当的测试图案并应用适当的测试策略来监测或控制制造环境对敏感屏障/种子材料系统的影响。 例如，可以制备实际的探针和参考基底并且可以在不暴露于感兴趣的制造环境的情况下进行处理，从而能够有效评估环境的一个或多个参数。 此外，可以基于本文公开的测试策略获得“优化的”制造环境。

公开(公告)号：US20080003826A1

公开(公告)日：2008-01-03

申请号：US11674869

申请日：2007-02-14

申请人： Thomas Werner ,  Robert Seidel ,  Frank Feustel

发明人： Thomas Werner ,  Robert Seidel ,  Frank Feustel

IPC分类号： H01L21/302

CPC分类号： H01L21/31144 ,  H01L21/31051 ,  H01L21/31053 ,  H01L21/31058 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76819

摘要： By additionally planarizing the surface topography of a planarization layer, which may be accomplished on the basis of mechanical contact, a uniform force, a polishing process and the like, an enhanced surface topography may be provided which may be advantageously used in subsequent patterning processes, such as photolithography, imprint techniques and the like.

摘要翻译： 通过额外地平坦化平面化层的表面形貌，其可以基于机械接触，均匀的力，抛光工艺等来实现，可以提供可以有利地用于随后的图案化工艺中的增强的表面形貌， 例如光刻，印记技术等。

公开(公告)号：US08039398B2

公开(公告)日：2011-10-18

申请号：US11866701

申请日：2007-10-03

申请人： Frank Feustel ,  Robert Seidel ,  Juergen Boemmels

发明人： Frank Feustel ,  Robert Seidel ,  Juergen Boemmels

IPC分类号： H01L21/302

CPC分类号： H01L21/3212

摘要： Prior to performing a CMP process for planarizing a metallization level of an advanced semiconductor device, an appropriate cap layer may be formed in order to delay the exposure of metal areas of reduced height level to the highly chemically reactive slurry material. Consequently, metal of increased height level may be polished with a high removal rate due to the mechanical and the chemical action of the slurry material, while the chemical interaction with the slurry material may be substantially avoided in areas of reduced height level. Therefore, a high process uniformity may be achieved even for pronounced initial surface topographies and slurry materials having a component of high chemical reactivity.

摘要翻译： 在执行用于平坦化先进半导体器件的金属化水平的CMP工艺之前，可以形成适当的盖层，以便将高度水平降低的金属区域暴露于高度化学反应性浆料材料。 因此，由于浆料的机械和化学作用，可以以高的去除速度抛光增加的高度水平的金属，同时可以在降低高度水平的区域中基本避免与浆料的化学相互作用。 因此，即使对于具有高化学反应性的组分的显着的初始表面形貌和浆料材料也可以获得高的工艺均匀性。

公开(公告)号：US20100164123A1

公开(公告)日：2010-07-01

申请号：US12640444

申请日：2009-12-17

申请人： Tobias Letz ,  Frank Feustel

发明人： Tobias Letz ,  Frank Feustel

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/76814 ,  H01L21/76826 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76886

摘要： Electromigration behavior in complex metallization systems of semiconductor devices may be enhanced at critical areas between a metal line and a via by locally forming a copper/silicon compound. In some illustrative embodiments, the formation of the copper/silicon compound may be combined with other treatments for cleaning the exposed surface areas and/or modifying the molecular structure thereof.

摘要翻译： 通过局部形成铜/硅化合物，可以在金属线和通孔之间的关键区域增强半导体器件复杂金属化系统中的电迁移行为。 在一些说明性实施例中，铜/硅化合物的形成可以与用于清洁暴露的表面区域和/或改变其分子结构的其它处理组合。

公开(公告)号：US20100052110A1

公开(公告)日：2010-03-04

申请号：US12505098

申请日：2009-07-17

申请人： Robert Seidel ,  Frank Feustel ,  Ralf Richter

发明人： Robert Seidel ,  Frank Feustel ,  Ralf Richter

IPC分类号： H01L23/48 ,  H01L21/98 ,  H01L21/60

CPC分类号： H01L21/76898 ,  H01L23/53276 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： In a semiconductor device, a through hole via extending through the substrate of the device may be formed on the basis of a carbon-containing material, thereby providing excellent compatibility with high temperature processes, while also providing superior electrical performance compared to doped semiconductor materials and the like. Thus, in some illustrative embodiments, the through hole vias may be formed prior to any process steps used for forming critical circuit elements, thereby substantially avoiding any interference of the through hole via structure with a device level of the corresponding semiconductor device. Consequently, highly efficient three-dimensional integration schemes may be realized.

摘要翻译： 在半导体器件中，可以基于含碳材料形成延伸穿过器件的衬底的通孔，从而与高温工艺相比具有优异的兼容性，同时与掺杂的半导体材料相比提供优异的电性能， 类似。 因此，在一些说明性实施例中，通孔过孔可以在用于形成关键电路元件的任何工艺步骤之前形成，从而基本上避免了通孔通孔结构与对应的半导体器件的器件级别的任何干扰。 因此，可以实现高效率的三维集成方案。

公开(公告)号：US20090085173A1

公开(公告)日：2009-04-02

申请号：US12056356

申请日：2008-03-27

申请人： Juergen Boemmels ,  Frank Feustel ,  Ralf Richter

发明人： Juergen Boemmels ,  Frank Feustel ,  Ralf Richter

IPC分类号： H01L23/58 ,  H01L21/311 ,  H01L21/44

CPC分类号： H01L23/53295 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： The present disclosure generally relates to forming a metallization layer in a semiconductor device. In particular, this disclosure concerns the damascene inlay technique in low-k dielectric layers. Etching trenches and vias in low-k dielectric materials leads to uneven and porous sidewalls of the trenches and vias due to the porous nature of the low-k dielectric materials. Thus, smooth and dense sidewalls cannot be achieved, which is a prerequisite for an effective barrier layer, which prevents copper from being diffused into the low-k dielectric material. As a consequence, process tolerances are high and the reliability of the semiconductor device is reduced. The present disclosure overcomes these drawbacks by a surface treatment of the sidewalls of trenches and vias in order to densify the surface such that the following barrier layer may more effectively prevent copper from diffusing into the low-k or ultra high-k dielectric material.

摘要翻译： 本公开一般涉及在半导体器件中形成金属化层。 特别地，本公开涉及在低k电介质层中的镶嵌技术。 由于低k介电材料的多孔性质，低k电介质材料中的蚀刻沟槽和通孔导致沟槽和通孔的不均匀和多孔的侧壁。 因此，不能实现平滑和致密的侧壁，这是有效阻挡层的先决条件，其阻止铜扩散到低k电介质材料中。 因此，工艺公差高，半导体器件的可靠性降低。 本公开通过沟槽和通孔的侧壁的表面处理克服了这些缺点，以便使表面致密化，使得后续阻挡层可以更有效地防止铜扩散到低k或超高k电介质材料中。

公开(公告)号：US20090032961A1

公开(公告)日：2009-02-05

申请号：US12036362

申请日：2008-02-25

申请人： Frank Feustel ,  Tobias Letz ,  Thomas Werner

发明人： Frank Feustel ,  Tobias Letz ,  Thomas Werner

IPC分类号： H01L21/768 ,  H01L23/538

CPC分类号： H01L23/5226 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76886 ,  H01L2924/0002 ,  H01L2924/00

摘要： By forming an alloy in a highly localized manner at a transition or contact area between a via and a metal line, the probability of forming an electromigration-induced shallow void may be significantly reduced, while not unduly affecting the overall electrical resistivity of the metal line. In one illustrative embodiment, an electroless deposition process may provide the alloy-forming species on the exposed metal region on the basis of an electroless plating process.

摘要翻译： 通过在通孔和金属线之间的过渡或接触区域以高度局部化的方式形成合金，可以显着减少形成电迁移诱导的浅空隙的可能性，同时不会过度地影响金属线的整体电阻率 。 在一个说明性实施例中，无电沉积工艺可以在无电镀工艺的基础上在暴露的金属区域上提供合金形成物质。

公开(公告)号：US20080265426A1

公开(公告)日：2008-10-30

申请号：US11943820

申请日：2007-11-21

申请人： Robert Seidel ,  Ralf Richter ,  Frank Feustel

发明人： Robert Seidel ,  Ralf Richter ,  Frank Feustel

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L21/7684 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76885

摘要： A method of forming a semiconductor structure comprises providing a substrate comprising a layer of a first material. A protection layer is formed over the layer of first material. At least one opening is formed in the layer of first material and the protection layer. A layer of a second material is formed over the layer of first material and the protection layer to fill the opening with the second material. A planarization process is performed to remove portions of the layer of second material outside the opening. At least a portion of the protection layer is not removed during the planarization process. An etching process is performed to remove the portions of the protection layer which were not removed during the planarization process.

摘要翻译： 一种形成半导体结构的方法包括提供包括第一材料层的衬底。 在第一材料层上形成保护层。 在第一材料层和保护层中形成至少一个开口。 在第一材料层上形成第二材料层，并且保护层用第二材料填充开口。 执行平面化处理以去除开口外部的第二材料层的部分。 在平坦化处理期间，保护层的至少一部分不被去除。 执行蚀刻处理以去除在平坦化处理期间未被去除的保护层的部分。

公开(公告)号：US07306976B2

公开(公告)日：2007-12-11

申请号：US11284292

申请日：2005-11-21

申请人： Frank Feustel ,  Matthias Lehr ,  Frank Kuechenmeister

发明人： Frank Feustel ,  Matthias Lehr ,  Frank Kuechenmeister

IPC分类号： H01L21/48

CPC分类号： H01L23/295 ,  H01L21/563 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： During the formation of an underfill material provided between a carrier substrate and a semiconductor chip, a common motion of particles contained in the underfill material is initiated towards the semiconductor chip, thereby adjusting the thermal and mechanical behavior of the underfill material. For instance, by applying an external force, such as gravity, a depletion zone with respect to the filler particles may be created in the vicinity of the carrier substrate, while a high particle concentration may be obtained in the vicinity of the semiconductor chip. Hence, thermal and mechanical stress redistribution by means of the underfill material may be enhanced.

摘要翻译： 在载体基板和半导体芯片之间形成的底部填充材料的形成期间，向底部填充材料中包含的颗粒的共同运动开始朝向半导体芯片，由此调整底部填充材料的热和机械性能。 例如，通过施加诸如重力的外力，可能在载体基板附近产生相对于填料颗粒的耗尽区，而在半导体芯片附近可以获得高的颗粒浓度。 因此，可以增强借助于底部填充材料的热和机械应力再分配。