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    Semiconductor device comprising self-aligned contact bars and metal lines with increased via landing regions
    2.
    发明授权
    Semiconductor device comprising self-aligned contact bars and metal lines with increased via landing regions 有权
    半导体器件包括自对准接触棒和具有增加的通过着陆区域的金属线

    公开(公告)号：US08399352B2

    公开(公告)日：2013-03-19

    申请号：US13331606

    申请日：2011-12-20

    申请人： Thomas Werner ,  Peter Baars ,  Frank Feustel

    发明人： Thomas Werner ,  Peter Baars ,  Frank Feustel

    IPC分类号： H01L21/4763

    CPC分类号： H01L23/5384 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/76816 ,  H01L23/5226 ,  H01L27/088 ,  H01L2924/0002 ,  H01L2924/00

    摘要： When forming metal lines of the metal zero level, a reduced bottom width and an increased top width may be achieved by using appropriate patterning regimes, for instance using a spacer structure after forming an upper trench portion with a top width, or forming the lower portion of the trenches and subsequently applying a further mask and etch regime in which the top width is implemented. In this manner, metal lines connecting to self-aligned contact bars may be provided so as to exhibit a bottom width of 20 nm and less, while the top width may allow reliable contact to any vias of the metallization system.

    摘要翻译： 当形成金属零电平的金属线时，可以通过使用适当的图案化方案来实现减小的底部宽度和增加的顶部宽度，例如在形成具有顶部宽度的上部沟槽部分之后使用间隔结构，或者形成下部 并且随后应用进一步实现顶部宽度的掩模和蚀刻方案。 以这种方式，可以提供连接到自对准接触棒的金属线，以便表现出20nm以下的底部宽度，而顶部宽度可以允许与金属化系统的任何通孔的可靠接触。

    SUPERIOR FILL CONDITIONS IN A REPLACEMENT GATE APPROACH BY USING A TENSILE STRESSED OVERLAYER
    3.
    发明申请
    SUPERIOR FILL CONDITIONS IN A REPLACEMENT GATE APPROACH BY USING A TENSILE STRESSED OVERLAYER 审中-公开
    采用拉伸应力覆盖层的替代浇口方法中的超级填充条件

    公开(公告)号：US20120223388A1

    公开(公告)日：2012-09-06

    申请号：US13471818

    申请日：2012-05-15

    申请人： Frank Feustel ,  Kai Frohberg ,  Thomas Werner

    发明人： Frank Feustel ,  Kai Frohberg ,  Thomas Werner

    IPC分类号： H01L27/088

    CPC分类号： H01L21/823807 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/7843

    摘要： In a replacement gate approach for forming high-k metal gate electrodes in semiconductor devices, a tapered configuration of the gate openings may be accomplished by using a tensile stressed dielectric material provided laterally adjacent to the gate electrode structure. Consequently, superior deposition conditions may be achieved while the tensile stress component may be efficiently used for the strain engineering in one type of transistor. Furthermore, an additional compressively stressed dielectric material may be applied after providing the replacement gate electrode structures.

    摘要翻译： 在用于在半导体器件中形成高k金属栅电极的替代栅极方法中，栅极开口的锥形配置可以通过使用横向邻近栅电极结构设置的拉应力电介质材料来实现。 因此，可以实现优异的沉积条件，同时可以有效地将拉伸应力分量用于一种类型的晶体管中的应变工程。 此外，可以在提供替换栅电极结构之后施加附加的压缩应力介电材料。

    Semiconductor Device Comprising Self-Aligned Contact Bars and Metal Lines With Increased Via Landing Regions
    4.
    发明申请
    Semiconductor Device Comprising Self-Aligned Contact Bars and Metal Lines With Increased Via Landing Regions 有权
    包括自对准接触棒和金属线路的半导体器件增加通过着陆区域

    公开(公告)号：US20120153366A1

    公开(公告)日：2012-06-21

    申请号：US13331606

    申请日：2011-12-20

    申请人： Thomas Werner ,  Peter Baars ,  Frank Feustel

    发明人： Thomas Werner ,  Peter Baars ,  Frank Feustel

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L23/5384 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/76816 ,  H01L23/5226 ,  H01L27/088 ,  H01L2924/0002 ,  H01L2924/00

    摘要： When forming metal lines of the metal zero level, a reduced bottom width and an increased top width may be achieved by using appropriate patterning regimes, for instance using a spacer structure after forming an upper trench portion with a top width, or forming the lower portion of the trenches and subsequently applying a further mask and etch regime in which the top width is implemented. In this manner, metal lines connecting to self-aligned contact bars may be provided so as to exhibit a bottom width of 20 nm and less, while the top width may allow reliable contact to any vias of the metallization system.

    摘要翻译： 当形成金属零电平的金属线时，可以通过使用适当的图案化方案来实现减小的底部宽度和增加的顶部宽度，例如在形成具有顶部宽度的上部沟槽部分之后使用间隔结构，或者形成下部 并且随后应用进一步实现顶部宽度的掩模和蚀刻方案。 以这种方式，可以提供连接到自对准接触棒的金属线，以便表现出20nm以下的底部宽度，而顶部宽度可以允许与金属化系统的任何通孔的可靠接触。

    SELF-ALIGNED CONTACT STRUCTURE LATERALLY ENCLOSED BY AN ISOLATION STRUCTURE OF A SEMICONDUCTOR DEVICE
    5.
    发明申请
    SELF-ALIGNED CONTACT STRUCTURE LATERALLY ENCLOSED BY AN ISOLATION STRUCTURE OF A SEMICONDUCTOR DEVICE 审中-公开
    通过半导体器件的隔离结构封装的自对准接触结构

    公开(公告)号：US20120021581A1

    公开(公告)日：2012-01-26

    申请号：US13237268

    申请日：2011-09-20

    申请人： Thomas Werner ,  Frank Feustel ,  Kai Frohberg

    发明人： Thomas Werner ,  Frank Feustel ,  Kai Frohberg

    IPC分类号： H01L21/336 ,  H01L21/762

    CPC分类号： H01L21/76897 ,  H01L21/28123 ,  H01L21/28518 ,  H01L21/76232

    摘要： By forming an isolation structure that extends above the height level defined by the semiconductor material of an active region, respective recesses may be defined in combination with gate electrode structures of the completion of basic transistor structures. These recesses may be subsequently filled with an appropriate contact material, thereby forming large area contacts in a self-aligned manner without requiring deposition and patterning of an interlayer dielectric material. Thereafter, the first metallization layer may be formed, for instance, on the basis of well-established techniques wherein the metal lines may connect directly to respective “large area” contact elements.

    摘要翻译： 通过形成在由有源区的半导体材料限定的高度水平之上延伸的隔离结构，相应的凹槽可以与完成基本晶体管结构的栅电极结构相结合。 这些凹部可以随后用适当的接触材料填充，从而以自对准的方式形成大面积的接触，而不需要层间绝缘材料的沉积和图案化。 此后，例如，可以基于公知的技术形成第一金属化层，其中金属线可以直接连接到相应的“大面积”接触元件。

    Test structure for monitoring leakage currents in a metallization layer
    7.
    发明授权
    Test structure for monitoring leakage currents in a metallization layer 有权
    用于监测金属化层中的漏电流的测试结构

    公开(公告)号：US07764078B2

    公开(公告)日：2010-07-27

    申请号：US11623372

    申请日：2007-01-16

    申请人： Frank Feustel ,  Thomas Werner ,  Carsten Peters

    发明人： Frank Feustel ,  Thomas Werner ,  Carsten Peters

    IPC分类号： G01R31/26 ,  G01R31/36 ,  H01L23/58

    CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    摘要： By providing a plurality of resistors and a plurality of test patterns within a leakage current test structure, the number of probe pads required for estimating the plurality of test patterns may be significantly reduced, wherein, in some illustrative embodiments, several test patterns may be simultaneously assessed on the basis of two probe pads. Consequently, process parameters and/or design parameters for manufacturing metallization structures of semiconductor devices may be efficiently monitored and controlled.

    摘要翻译： 通过在泄漏电流测试结构内提供多个电阻器和多个测试图案，可以显着地减少用于估计多个测试图案所需的探针焊盘的数量，其中在一些说明性实施例中，可以同时进行几个测试图案 基于两个探针垫进行评估。 因此，可以有效地监测和控制用于制造半导体器件的金属化结构的工艺参数和/或设计参数。

    MICROSTRUCTURE DEVICE INCLUDING A METALLIZATION STRUCTURE WITH SELF-ALIGNED AIR GAPS BETWEEN CLOSELY SPACED METAL LINES
    9.
    发明申请
    MICROSTRUCTURE DEVICE INCLUDING A METALLIZATION STRUCTURE WITH SELF-ALIGNED AIR GAPS BETWEEN CLOSELY SPACED METAL LINES 审中-公开
    微结构装置，其中包括在相互间隔的金属线之间具有自对准空气GAPS的金属化结构

    公开(公告)号：US20090294898A1

    公开(公告)日：2009-12-03

    申请号：US12400983

    申请日：2009-03-10

    申请人： Frank Feustel ,  Thomas Werner ,  Kai Frohberg

    发明人： Frank Feustel ,  Thomas Werner ,  Kai Frohberg

    IPC分类号： H01L23/58 ,  H01L21/764

    CPC分类号： H01L21/7682 ,  H01L21/76885

    摘要： Air gaps may be provided in a self-aligned manner with sub-lithography resolution between closely spaced metal lines of sophisticated metallization systems of semiconductor devices by recessing the dielectric material in the vicinity of the metal lines and forming respective sidewall spacer elements. Thereafter, the spacer elements may be used as an etch mask so as to define the lateral dimension of a gap on the basis of the corresponding air gaps, which may then be obtained by depositing a further dielectric material.

    摘要翻译： 可以通过在金属线附近凹陷介电材料并形成相应的侧壁间隔元件，以自对准的方式提供半空间复杂金属化系统的紧密间隔金属线之间的亚光刻分辨率的气隙。 此后，间隔元件可以用作蚀刻掩模，以便基于相应的气隙限定间隙的横向尺寸，然后可以通过沉积另外的电介质材料来获得。