公开(公告)号：US20110006362A1

公开(公告)日：2011-01-13

申请号：US12458400

申请日：2009-07-10

申请人： Fu-Yuan Hsieh

发明人： Fu-Yuan Hsieh

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7811 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

摘要： A trench MOSFET with on-resistance reduction comprises a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate, wherein the said MOSFET further comprises a plurality of source-body contact trenches opened relative to a top surface into said source and body regions and each of the source-body contact trenches is filled with a contact metal plug as a source-body contact; a insulation layer covered over the top of the trenched gate, the body region and the source region; a front metal layer formed on a top surface of the MOSFET; wherein a low-resistivity phosphorus substrate and retrograded P-body formed by medium or high energy Ion Implantation to reduce Rds contribution from substrate and drift region.

摘要翻译： 具有导通电阻降低的沟槽MOSFET包括被包围在设置在衬底的底表面上的漏极区域上方的体区中的源极区包围的沟槽栅极，其中所述MOSFET还包括多个源体接触沟槽， 相对于进入所述源体和体区的顶表面，并且每个源体接触沟被填充有作为源体接触的接触金属塞; 覆盖在所述沟槽栅极的顶部，所述主体区域和所述源极区域上的绝缘层; 形成在所述MOSFET的顶表面上的前金属层; 其中通过中等或高能量离子注入形成的低电阻率磷基底和退化的P体以减少由底物和漂移区域引起的Rds贡献。

公开(公告)号：US20100289073A1

公开(公告)日：2010-11-18

申请号：US12453631

申请日：2009-05-18

申请人： Fu-Yuan Hsieh

发明人： Fu-Yuan Hsieh

IPC分类号： H01L29/78 ,  H01L21/762

CPC分类号： H01L29/7813 ,  H01L27/0255 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/866

摘要： A semiconductor power device with Zener diode for providing an electrostatic discharge (ESD) protection and a thick insulation layer to insulate the Zener diode from a doped body region. The semiconductor power device further includes a Nitride layer underneath the thick oxide layer working as a stopper layer for protecting the thin oxide layer and the body region underneath whereby the over-etch damage and punch-through issues in process steps are eliminated.

摘要翻译： 具有用于提供静电放电（ESD）保护的齐纳二极管的半导体功率器件和用于使齐纳二极管与掺杂体区域绝缘​​的厚绝缘层。 半导体功率器件还包括在厚氧化物层下面的氮化物层，其作为用于保护薄氧化物层和下面的体区的阻挡层，由此消除了工艺步骤中的过蚀刻损坏和穿通问题。

公开(公告)号：US07816732B2

公开(公告)日：2010-10-19

申请号：US12213628

申请日：2008-06-23

申请人： Fu-Yuan Hsieh

发明人： Fu-Yuan Hsieh

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L27/0629 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/8725

摘要： A trench MOSFET in parallel with trench Schottky barrier rectifier is formed on a single substrate. The present invention solves the constrains brought by planar contact of Schottky, for example, the large area occupied by planar structure. As the size of present device is getting smaller and smaller, the trench Schottky structure of this invention is able to be shrink and, at the same time, to achieve low specific on-resistance. By applying a double epitaxial layer in trench Schottky barrier rectifier, the device performance is enhanced for lower Vf and lower reverse leakage current Ir is achieved.

摘要翻译： 与沟槽肖特基势垒整流器并联的沟槽MOSFET形成在单个衬底上。 本发明解决了由肖特基的平面接触引起的约束，例如由平面结构占据的大面积。 随着本装置的尺寸越来越小，本发明的沟槽肖特基结构能够收缩，并且同时实现低的比导通电阻。 通过在沟道肖特基势垒整流器中施加双重外延层，器件性能随着Vf的降低而提高，并且实现了较低的反向漏电流Ir。

公开(公告)号：US07791136B1

公开(公告)日：2010-09-07

申请号：US12385891

申请日：2009-04-23

申请人： Fu-Yuan Hsieh

发明人： Fu-Yuan Hsieh

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/872 ,  H01L29/8725

摘要： An integrated configuration comprising trench MOSFET having trench contacts and trench Schottky rectifier having planar contacts is disclosed. The trench contacts for trench MOSFET provide a lower specific on-resistance. Besides, for trench gate connection, planar gate contact is employed in the present invention to avoid shortage issue between gate and drain in shallow trench gate. Besides, W plugs filled into both trench contacts and planar contacts enhance the metal step coverage capability.

摘要翻译： 公开了一种集成配置，其包括具有沟槽触点的沟槽MOSFET和具有平面触点的沟槽肖特基整流器。 沟槽MOSFET的沟槽触点提供较低的导通电阻。 此外，对于沟槽栅极连接，在本发明中采用平面栅极接触，以避免浅沟槽栅极中栅极和漏极之间的短缺问题。 此外，填充在沟槽触点和平面触点中的W插头增强了金属台阶覆盖能力。

公开(公告)号：US20100072543A1

公开(公告)日：2010-03-25

申请号：US12137527

申请日：2008-09-25

申请人： Fu-Yuan Hsieh

发明人： Fu-Yuan Hsieh

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/4925 ,  H01L29/4941 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： The present invention is to provide a trench MOSFET with an etching buffer layer in a trench gate, comprising: a substrate which has a first surface and a second surface opposite to each other and comprises at least a drain region, a gate region, and a source region which are constructed as a plurality of semiconductor cells with MOSFET effect; a plurality of gate trenches, each of which is extended downward from the first surface and comprises a gate oxide layer covered on a inner surface thereof and a gate conductive layer filled inside, comprised in the gate region; at least a drain metal layer formed on the second surface according to the drain region; at least a gate runner metal layer formed on the first surface according to the gate region; and at least a source metal layer formed on the first surface according to the source region; wherein the gate trenches distinguished into at least a second gate trench formed at a terminal of the source region and at least a first gate trenches wrapped in the source region; and the second gate trench comprises a gate contact hole which is filled with metal to form a gate metal contact plug, and a gate buffer layer which is formed in the gate conductive layer at the bottom of the gate contact hole in the second gate trench to prevent from over etching, causing gate-drain shortage.

摘要翻译： 本发明提供一种在沟槽栅极中具有蚀刻缓冲层的沟槽MOSFET，包括：衬底，其具有彼此相对的第一表面和第二表面，并且至少包括漏极区域，栅极区域和 源区，其被构造为具有MOSFET效应的多个半导体单元; 多个栅极沟槽，每个栅极沟槽从第一表面向下延伸，并且包括在其内表面上覆盖的栅极氧化物层和填充在栅极区域中的内部的栅极导电层; 至少漏极金属层，根据所述漏极区域形成在所述第二表面上; 至少一个闸门金属层，根据栅极区形成在第一表面上; 以及至少源极金属层，所述源极金属层根据所述源极区域形成在所述第一表面上; 其中所述栅极沟槽区分为形成在所述源极区域的端子处的至少第二栅极沟槽和至少包围在所述源极区域中的第一栅极沟槽; 并且所述第二栅极沟槽包括填充有金属以形成栅极金属接触插塞的栅极接触孔和形成在所述栅极导电层中的所述栅极缓冲层中，所述栅极缓冲层位于所述第二栅极沟槽中的所述栅极接触孔的底部， 防止过蚀刻，引起漏水不足。

公开(公告)号：US20090309181A1

公开(公告)日：2009-12-17

申请号：US12137550

申请日：2008-06-12

申请人： Fu-Yuan Hsieh

发明人： Fu-Yuan Hsieh

IPC分类号： H01L29/47

CPC分类号： H01L29/872 ,  H01L29/0611 ,  H01L29/8725

摘要： A trench Schottky barrier rectifier includes an cathode electrode at a face of a semiconductor substrate and an multiple epitaxial structure in drift region which in combination provide high blocking voltage capability with low reverse-biased leakage current and low forward voltage. The multiple structure of the drift region contains a concentration of first conductivity dopants therein which comprises two or three different uniform value from a Schottky rectifying junction formed between the anode electrode and the drift region. The thickness of the insulating region (e.g., SiO2) in the MOS-filled trenches is greater than 1000 Å to simultaneously inhibit field crowing and increase the breakdown voltage of the device. The multiple epi structure is preferably formed by epitaxial growth from the cathode region and doped in-situ.

摘要翻译： 沟道肖特基势垒整流器包括在半导体衬底的表面处的阴极电极和漂移区域中的多个外延结构，其组合提供具有低反向偏置漏电流和低正向电压的高阻断电压能力。 漂移区的多重结构包含其中的第一导电性掺杂剂的浓度，其包含来自形成在阳极电极和漂移区域之间的肖特基整流结的两个或三个不同的均匀值。 MOS填充的沟槽中的绝缘区域（例如SiO 2）的厚度大于1000，以同时抑制场强挤压并增加器件的击穿电压。 多个epi结构优选通过从阴极区域外延生长并原位掺杂形成。

公开(公告)号：US20080169505A1

公开(公告)日：2008-07-17

申请号：US11847445

申请日：2007-08-30

申请人： Fu-Yuan Hsieh

发明人： Fu-Yuan Hsieh

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/743 ,  H01L29/41741 ,  H01L29/42376 ,  H01L29/456 ,  H01L29/4941 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A trench MOSFET with copper metal connections is disclosed. A substrate is provided with a plurality of trenches. A gate oxide layer is formed on the sidewalls and bottoms of the trenches. A conductive layer is filled in the trenches to be used as a gate of the MOSFET. A plurality of source and body regions are formed in an epi layer. An insulating layer is formed on the epi layer and formed with a plurality of metal contact holes therein for contacting respective source and body regions. A barrier metal layer is formed on the sidewalls and bottoms of the metal contact holes in direct contact with respective source and body regions. A metal contact layer is filled in the metal contact holes. A copper metal layer is formed on another barrier metal layer on the insulating layer connected to respective source regions through the metal contact layer to form metal connections of the MOSFET.

摘要翻译： 公开了一种具有铜金属连接的沟槽MOSFET。 衬底设置有多个沟槽。 栅极氧化层形成在沟槽的侧壁和底部上。 在沟槽中填充导电层以用作MOSFET的栅极。 在外延层中形成多个源极和主体区域。 在外延层上形成绝缘层，并在其中形成有多个金属接触孔，以使各个源极和体区接触。 在金属接触孔的侧壁和底部上形成阻挡金属层，其与相应的源极和主体区域直接接触。 金属接触层填充在金属接触孔中。 在通过金属接触层连接到各个源极区域的绝缘层上的另一阻挡金属层上形成铜金属层，以形成MOSFET的金属连接。

公开(公告)号：US08816348B2

公开(公告)日：2014-08-26

申请号：US13186615

申请日：2011-07-20

申请人： Fu-Yuan Hsieh

发明人： Fu-Yuan Hsieh

IPC分类号： H01L27/06

CPC分类号： H01L29/7813 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/407 ,  H01L29/7806 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/861 ,  H01L29/872 ,  H01L29/8725

摘要： A trench shielded gate MOSFET device with embedded Schottky rectifier, Gate-Drain and Gate-Source clamp diodes on single chip is formed to achieve device shrinkage, lower cost and improved performance. The present semiconductor device achieve low Vf and reverse leakage current for embedded Schottky rectifier, having over-voltage protection and avalanche protection between gate and source and between gate and drain.

摘要翻译： 形成了具有嵌入式肖特基整流器，单芯片上的栅极 - 漏极和栅极 - 源极钳位二极管的沟槽屏蔽栅极MOSFET器件，以实现器件收缩，降低成本并提高性能。 本半导体器件实现嵌入式肖特基整流器的低Vf和反向漏电流，具有栅极和源极之间以及栅极和漏极之间的过压保护和雪崩保护。

公开(公告)号：US08723317B2

公开(公告)日：2014-05-13

申请号：US13616384

申请日：2012-09-14

申请人： Fu-Yuan Hsieh

发明人： Fu-Yuan Hsieh

IPC分类号： H01L23/48 ,  H01L23/34 ,  H01L23/52 ,  H01L21/00

CPC分类号： H01L29/66666 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/00

摘要： A trench MOSFET with embedded schottky rectifier having at least one anti-punch through implant region using reduced masks process is disclosed for avalanche capability enhancement and cost reduction. The source regions have a higher doping concentration and a greater junction depth along sidewalls of the trenched source-body contacts than along adjacent channel regions near the gate trenches.

摘要翻译： 公开了具有嵌入肖特基整流器的沟槽MOSFET，其具有使用减少的掩模工艺的至少一个抗穿通注入区域，用于雪崩能力增强和成本降低。 源极区域沿着沟槽源极体接触的侧壁具有比沿着栅极沟槽附近的相邻沟道区域更高的掺杂浓度和更大的结深度。

公开(公告)号：US08652900B2

公开(公告)日：2014-02-18

申请号：US13441967

申请日：2012-04-09

申请人： Fu-Yuan Hsieh

发明人： Fu-Yuan Hsieh

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7808 ,  H01L29/7811

摘要： A trench MOSFET structure with ultra high cell density is disclosed, wherein the source regions and the body regions are located in different regions to save the mesa area between every two adjacent gate trenches in the active area. Furthermore, the inventive trench MOSFET is composed of stripe cells to further increase cell packing density and decrease on resistance Rds between the drain region and the source region.

摘要翻译： 公开了一种具有超高电池密度的沟槽MOSFET结构，其中源极区域和主体区域位于不同的区域中以节省有源区域中每两个相邻栅极沟槽之间的台面面积。 此外，本发明的沟槽MOSFET由条形电池组成，以进一步增加电池堆积密度并降低漏极区域和源极区域之间的导通电阻Rds。