公开(公告)号：US08658492B2

公开(公告)日：2014-02-25

申请号：US13542753

申请日：2012-07-06

申请人： Fu-Yuan Hsieh

发明人： Fu-Yuan Hsieh

IPC分类号： H01L27/06

CPC分类号： H01L29/7813 ,  H01L27/0255 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/407 ,  H01L29/417 ,  H01L29/41766 ,  H01L29/66106 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/866

摘要： A semiconductor power device integrated with ESD protection diode is disclosed by offering a dopant out-diffusion suppression layers prior to source dopant activation or diffusion to enhance ESD protection capability between gate and source.

摘要翻译： 通过在源掺杂剂激活或扩散之前提供掺杂剂外扩散抑制层来增强与ESD保护二极管集成的半导体功率器件，以增强栅极和源极之间的ESD保护能力。

公开(公告)号：US08653589B2

公开(公告)日：2014-02-18

申请号：US13196324

申请日：2011-08-02

申请人： Fu-Yuan Hsieh

发明人： Fu-Yuan Hsieh

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/872 ,  H01L29/8725

摘要： An integrated circuit includes a plurality of trench MOSFET and a plurality of trench Schottky rectifier. The integrated circuit further comprises: tilt-angle implanted body dopant regions surrounding a lower portion of all trenched gates sidewalls for reducing Qgd; a source dopant region disposed below trench bottoms of all trenched gates for functioning as a current path for preventing a resistance increased caused by the tilt-angle implanted body dopant regions.

摘要翻译： 集成电路包括多个沟槽MOSFET和多个沟槽肖特基整流器。 集成电路还包括：围绕所有沟槽门侧壁的下部的倾斜角植入体掺杂区，用于减少Qgd; 源掺杂区域，其设置在所有沟槽栅极的沟槽底部下方，用作电流路径，用于防止由倾斜角植入体掺杂区域引起的电阻增加。

公开(公告)号：US08563381B2

公开(公告)日：2013-10-22

申请号：US13585059

申请日：2012-08-14

申请人： Fu-Yuan Hsieh

发明人： Fu-Yuan Hsieh

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0626 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7808

摘要： A power semiconductor device with improved avalanche capability structures is disclosed. By forming at least an avalanche capability enhancement doped regions with opposite conductivity type to epitaxial layer underneath an ohmic contact doped region which surrounds at least bottom of trenched contact filled with metal plug between two adjacent gate trenches, avalanche current is enhanced with the disclosed structures.

摘要翻译： 公开了一种具有改进的雪崩能力结构的功率半导体器件。 通过至少形成具有相反导电类型的雪崩能力增强掺杂区域，该外延层在欧姆接触掺杂区域之下，该欧姆接触掺杂区域至少包围填充有两个相邻栅极沟槽之间的金属插塞的沟槽触点的底部，所公开的结构增强了雪崩电流。

公开(公告)号：US08466514B2

公开(公告)日：2013-06-18

申请号：US13274642

申请日：2011-10-17

申请人： Fu-Yuan Hsieh

发明人： Fu-Yuan Hsieh

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L27/0255 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/407 ,  H01L29/417 ,  H01L29/41766 ,  H01L29/7397 ,  H01L29/7803 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/866 ,  H01L2224/02166 ,  H01L2924/13055 ,  H01L2924/00

摘要： A trench semiconductor power device integrated with four types of ESD clamp diodes for optimization of total perimeter of the ESD clamp diodes, wherein the ESD clamp diodes comprise multiple back to back Zener diodes with alternating doped regions of a first conductivity type next to a second conductivity type, wherein each of the doped regions has a closed ring structure.

摘要翻译： 一种与四种类型的ESD钳位二极管集成的沟槽半导体功率器件，用于优化ESD钳位二极管的总周边，其中ESD钳位二极管包括多个背靠背齐纳二极管，其具有紧邻第二导电性的第一导电类型的交替掺杂区域 型，其中每个掺杂区具有闭环结构。

公开(公告)号：US08378411B2

公开(公告)日：2013-02-19

申请号：US13070755

申请日：2011-03-24

申请人： Fu-Yuan Hsieh

发明人： Fu-Yuan Hsieh

IPC分类号： H01L29/76 ,  H01L31/062

CPC分类号： H01L27/0629 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0255 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/7397 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7821 ,  H01L29/866 ,  H01L2224/04042 ,  H01L2224/05 ,  H01L2224/05552 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4813 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2924/01005 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/12035 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A structure of power semiconductor device integrated with clamp diodes having separated gate metal pads is disclosed. The separated gate metal pads are wire bonded together on the gate lead frame. This improved structure can prevent the degradation of breakdown voltage due to electric field in termination region blocked by polysilicon or gate metal.

摘要翻译： 公开了与具有分离的栅极金属焊盘的钳位二极管集成的功率半导体器件的结构。 分离的栅极金属焊盘在栅极引线框架上引线接合在一起。 这种改进的结构可以防止由于多晶硅或栅极金属阻塞的端接区域中的电场引起的击穿电压的劣化。

公开(公告)号：US08373224B2

公开(公告)日：2013-02-12

申请号：US13291442

申请日：2011-11-08

申请人： Fu-Yuan Hsieh

发明人： Fu-Yuan Hsieh

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A super-junction trench MOSFET with Resurf Stepped Oxide and trenched contacts is disclosed. The inventive structure can apply additional freedom for better optimization and manufacturing capability by tuning thick oxide thickness to minimize influence of charge imbalance, trapped charges, etc. . . . Furthermore, the fabrication method can be implemented more reliably with lower cost.

摘要翻译： 公开了具有Resurf步进氧化物和沟槽触点的超结沟槽MOSFET。 本发明的结构可以通过调整厚的氧化物厚度以最小化电荷不平衡，被捕获的电荷等的影响来应用额外的自由度来获得更好的优化和制造能力。 。 。 此外，可以以更低的成本更可靠地实现制造方法。

公开(公告)号：US08314000B2

公开(公告)日：2012-11-20

申请号：US13006556

申请日：2011-01-14

申请人： Fu-Yuan Hsieh

发明人： Fu-Yuan Hsieh

IPC分类号： H01L21/336

CPC分类号： H01L29/0847 ,  H01L21/26586 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66659 ,  H01L29/7835

摘要： A LDMOS with double LDD and trenched drain is disclosed. According to some preferred embodiment of the present invention, the structure contains a double LDD region, including a high energy implantation to form lightly doped region and a low energy implantation thereon to provide a low resistance path for current flow without degrading breakdown voltage. At the same time, a P+ junction made by source mask is provided underneath source region to avoid latch-up effect from happening.

公开(公告)号：US08269273B2

公开(公告)日：2012-09-18

申请号：US12137527

申请日：2008-09-25

申请人： Fu-Yuan Hsieh

发明人： Fu-Yuan Hsieh

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/4925 ,  H01L29/4941 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： The present invention is to provide a trench MOSFET with an etching buffer layer in a trench gate, comprising: a substrate which has a first surface and a second surface opposite to each other and comprises at least a drain region, a gate region, and a source region which are constructed as a plurality of semiconductor cells with MOSFET effect; a plurality of gate trenches, each of which is extended downward from the first surface and comprises a gate oxide layer covered on a inner surface thereof and a gate conductive layer filled inside, comprised in the gate region; at least a drain metal layer formed on the second surface according to the drain region; at least a gate runner metal layer formed on the first surface according to the gate region; and at least a source metal layer formed on the first surface according to the source region; wherein the gate trenches distinguished into at least a second gate trench formed at a terminal of the source region and at least a first gate trenches wrapped in the source region; and the second gate trench comprises a gate contact hole which is filled with metal to form a gate metal contact plug, and a gate buffer layer which is formed in the gate conductive layer at the bottom of the gate contact hole in the second gate trench to prevent from over etching, causing gate-drain shortage.

摘要翻译： 本发明提供一种在沟槽栅极中具有蚀刻缓冲层的沟槽MOSFET，包括：衬底，其具有彼此相对的第一表面和第二表面，并且至少包括漏极区域，栅极区域和 源区，其被构造为具有MOSFET效应的多个半导体单元; 多个栅极沟槽，每个栅极沟槽从第一表面向下延伸，并且包括在其内表面上覆盖的栅极氧化物层和填充在栅极区域中的内部的栅极导电层; 至少漏极金属层，根据所述漏极区域形成在所述第二表面上; 至少一个闸门金属层，根据栅极区形成在第一表面上; 以及至少源极金属层，所述源极金属层根据所述源极区域形成在所述第一表面上; 其中所述栅极沟槽区分为形成在所述源极区域的端子处的至少第二栅极沟槽和至少包围在所述源极区域中的第一栅极沟槽; 并且所述第二栅极沟槽包括填充有金属以形成栅极金属接触插塞的栅极接触孔和形成在所述栅极导电层中的所述栅极缓冲层中，所述栅极缓冲层位于所述第二栅极沟槽中的所述栅极接触孔的底部， 防止过蚀刻，引起漏水不足。

公开(公告)号：US08105903B2

公开(公告)日：2012-01-31

申请号：US12585645

申请日：2009-09-21

申请人： Fu-Yuan Hsieh

发明人： Fu-Yuan Hsieh

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A method for making a trench MOSFET with shallow trench structures with a thick trench bottom is disclosed. The improved method resolves the problem of deterioration of breakdown voltage resulted by LOCOS having a bird's beak shape introduced in prior art, and at the same time, the inventive device has a lower Qgd and lower Rds.

摘要翻译： 公开了一种用于制造具有厚沟槽底部的具有浅沟槽结构的沟槽MOSFET的方法。 改进的方法解决了现有技术中引入的具有鸟喙形状的LOCOS导致的击穿电压劣化的问题，同时本发明的器件具有较低的Qgd和较低的Rds。

公开(公告)号：US20110254071A1

公开(公告)日：2011-10-20

申请号：US13169340

申请日：2011-06-27

申请人： Fu-Yuan Hsieh

发明人： Fu-Yuan Hsieh

IPC分类号： H01L29/788

CPC分类号： H01L29/7813 ,  H01L21/823481 ,  H01L21/823487 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7811

摘要： A trench MOSFET comprising a plurality of transistor cells having shielded trenched gates and multiple trenched floating gates as termination region is disclosed. The trenched floating gates have trench depth equal to or deeper than body junction depth of body regions in termination area. In some preferred embodiments, the trenched floating gates in the termination area are implemented by using shielded electrode structure.