公开(公告)号：US09330971B2

公开(公告)日：2016-05-03

申请号：US14195932

申请日：2014-03-04

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Scott Beasor ,  Jagar Singh

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/50 ,  H01L27/06 ,  H01L21/8234

CPC classification number: H01L21/76877 ,  H01L21/76802 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/845 ,  H01L23/481 ,  H01L23/50 ,  H01L23/5228 ,  H01L27/0629 ,  H01L27/1211 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes etching an ILD layer of dielectric material overlying a semiconductor substrate that includes a device region to form first contact vias that expose active areas of the device region. The ILD layer is etched to form second contact vias that correspondingly expose a gate that is disposed in the device region and a patterned resistive metal-containing layer that is disposed in the ILD layer adjacent to the device region. The first contact vias and the second contact vias are filled with an electrically-conductive material to form first contacts that are in electrical communication with the active areas and second contacts that include a gate contact and a metal resistor contact that are in electrical communication with the gate and the patterned resistive metal-containing layer, respectively.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个示例中，制造集成电路的方法包括蚀刻覆盖在半导体衬底上的介电材料的ILD层，其包括器件区域，以形成暴露器件区域的有源区域的第一接触孔。 ILD层被蚀刻以形成相应地暴露设置在器件区域中的栅极的第二接触孔，以及设置在与器件区域相邻的ILD层中的图案化的含电阻金属层。 第一接触通孔和第二接触通孔被填充有导电材料，以形成与有源区和第二接触电连通的第一接触，第二接触包括栅接触和金属电阻接触， 栅极和图案化的含电阻金属层。

公开(公告)号：US09324827B1

公开(公告)日：2016-04-26

申请号：US14525744

申请日：2014-10-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Jerome Ciavatti

IPC: H01L29/66 ,  H01L29/872 ,  H01L29/06

CPC classification number: H01L29/66143 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0629 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/872

Abstract: A non-planar Schottky diode includes a semiconductor substrate of a first type, the first type including one of n-type and p-type. The structure further includes raised semiconductor structure(s) of a second type opposite the first type coupled to the substrate, isolation material surrounding a lower portion of the raised structure(s), a first well of the second type directly under the raised structure(s), a guard ring of the first type around an edge of a top portion of the first well, a conformal layer of silicide over a top portion of the raised structure(s) above the isolation material, and a common contact above the conformal layer of silicide. The non-planar Schottky diode can be fabricated with non-planar transistors, e.g., FinFETs.

Abstract translation: 非平面肖特基二极管包括第一类型的半导体衬底，第一类型包括n型和p型之一。 该结构还包括与耦合到衬底的第一类型相反的第二类型的凸起半导体结构，围绕凸起结构的下部的隔离材料，直立在凸起结构下方的第二类型的第一阱（ s），围绕第一阱的顶部的边缘的第一类型的保护环，在隔离材料上方的凸起结构的顶部上的硅化物的保形层，以及在保形层之上的公共接触 硅化物层。 非平面肖特基二极管可以用非平面晶体管制造，例如FinFET。

公开(公告)号：US09276088B1

公开(公告)日：2016-03-01

申请号：US14515070

申请日：2014-10-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh

IPC: H01L21/8242 ,  H01L29/66 ,  H01L27/088 ,  H01L21/762

CPC classification number: H01L27/0886 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0684 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66795

Abstract: Methods for making high voltage IC devices utilizing a fin-type process and resulting devices are disclosed. Embodiments include forming two pluralities of silicon fins on a substrate layer, separated by a space, wherein adjacent silicon fins are separated by a trench; forming an oxide layer on the substrate layer and filling a portion of each trench; forming two deep isolation trenches into the oxide layer and the substrate layer adjacent to the two pluralities of silicon fins; forming a graded voltage junction by implanting a dopant into the substrate layer below the two pluralities of silicon fins; forming a gate structure on the oxide layer and between the two pluralities of silicon fins; implanting a dopant into and under the two pluralities of silicon fins, forming source and drain regions; and forming an epitaxial layer onto the two pluralities of silicon fins to form merged source and drain fins.

公开(公告)号：US09230913B1

公开(公告)日：2016-01-05

申请号：US14457155

申请日：2014-08-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Biswanath Senapati ,  Jagar Singh ,  Karthik Chandrasekaran

IPC: H01L21/30 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Structures and methods to minimize parasitic capacitance in a circuit structure are provided. The structure may include a substrate supporting one or more circuits and one or more metallization layers above the substrate. The metallization layer includes a conductive pattern defined by an array of conductive fill elements, where the conductive fill elements of the array are discrete, electrically isolated elements sized to satisfy, at least in part, a pre-defined minimum area-occupation ratio for a chemical-mechanical polishing of the metallization layer, and to minimize parasitic capacitance within the metallization layer, as well as minimize parasitic capacitance between the metallization layer and the circuit, and if multiple metallization layers are present, between the layers.

Abstract translation: 提供了使电路结构中的寄生电容最小化的结构和方法。 该结构可以包括支撑一个或多个电路的衬底和在衬底上方的一个或多个金属化层。 金属化层包括由导电填充元件阵列限定的导电图案，其中阵列的导电填充元件是离散的，电隔离的元件，其大小至少部分地满足预定义的最小面积占有率 金属化层的化学机械抛光，并且使金属化层内的寄生电容最小化，以及最小化金属化层和电路之间的寄生电容，以及如果存在多个金属化层，则在层之间。

公开(公告)号：US20150255335A1

公开(公告)日：2015-09-10

申请号：US14195932

申请日：2014-03-04

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Scott Beasor ,  Jagar Singh

IPC: H01L21/768 ,  H01L49/02 ,  H01L23/50 ,  H01L27/06 ,  H01L23/48

CPC classification number: H01L21/76877 ,  H01L21/76802 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/845 ,  H01L23/481 ,  H01L23/50 ,  H01L23/5228 ,  H01L27/0629 ,  H01L27/1211 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes etching an ILD layer of dielectric material overlying a semiconductor substrate that includes a device region to form first contact vias that expose active areas of the device region. The ILD layer is etched to form second contact vias that correspondingly expose a gate that is disposed in the device region and a patterned resistive metal-containing layer that is disposed in the ILD layer adjacent to the device region. The first contact vias and the second contact vias are filled with an electrically-conductive material to form first contacts that are in electrical communication with the active areas and second contacts that include a gate contact and a metal resistor contact that are in electrical communication with the gate and the patterned resistive metal-containing layer, respectively.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个示例中，制造集成电路的方法包括蚀刻覆盖在半导体衬底上的介电材料的ILD层，其包括器件区域，以形成暴露器件区域的有源区域的第一接触孔。 ILD层被蚀刻以形成相应地暴露设置在器件区域中的栅极的第二接触孔，以及设置在与器件区域相邻的ILD层中的图案化的含电阻金属层。 第一接触通孔和第二接触通孔被填充有导电材料，以形成与有源区和第二接触电连通的第一接触，第二接触包括栅接触和金属电阻接触， 栅极和图案化的含电阻金属层。

公开(公告)号：US20150001630A1

公开(公告)日：2015-01-01

申请号：US13929165

申请日：2013-06-27

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jagar Singh

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/092

CPC classification number: H01L29/66795 ,  H01L29/0657 ,  H01L29/1037 ,  H01L29/785

Abstract: A semiconductor FinFET device in fabrication includes a semiconductor substrate and at least one semiconductor fin coupled to the substrate. Each of the semiconductor fins further include a single drain branch coupled to at least two source branches at a common area, with the two source branches acting together as a source. A channel area is situated in the common area. In one example, the single drain branch and two source branches are coupled at the common area to form a generally Y-shaped fin. Further fabrication to complete the FinFET may then proceed.

Abstract translation: 半导体FinFET器件的制造包括半导体衬底和耦合到衬底的至少一个半导体鳍片。 每个半导体鳍片还包括耦合到共同区域处的至少两个源极分支的单个漏极分支，两个源极分支作为源极一起起作用。 通道区位于公共区域。 在一个示例中，单个漏极分支和两个源极分支在公共区域耦合以形成大致Y形的翅片。 可以进一步完成FinFET的制造。

公开(公告)号：US20140231960A1

公开(公告)日：2014-08-21

申请号：US13767930

申请日：2013-02-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Nam Sung Kim ,  Roderick M. Miller ,  Shesh M. Pandey ,  Jagar Singh

IPC: H01L49/02

CPC classification number: H01L28/20

Abstract: Aspects of the present invention relate to an approach for implanting and forming a polysilicon resistor with a single implant dose. Specifically, a mask having a set of openings is formed over a resistor surface. The set of openings are typically formed in a column-row arrangement according to a predetermined pattern. Forming the mask in this manner allows the resistor surface to have multiple regions/zones. A first region is defined by the set of openings in the mask, and a second region is defined by the remaining portions of the mask. The resistor is then subjected to a single implant dose via the openings. Implanting the resistor in this manner allows the resistor to have multiple resistance values (i.e., a first resistance value in the first region, and a second resistance value in the second region).

Abstract translation: 本发明的各方面涉及用单一注入剂量植入和形成多晶硅电阻器的方法。 具体地，在电阻表面上形成具有一组开口的掩模。 一组开口通常根据预定图案以列排布置形成。 以这种方式形成掩模允许电阻器表面具有多个区域/区域。 第一区域由掩模中的开口组限定，第二区域由掩模的其余部分限定。 然后通过开口对电阻器进行单次注入剂量。 以这种方式植入电阻器，电阻器具有多个电阻值（即，第一区域中的第一电阻值，以及第二区域中的第二电阻值）。