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145 条记录 (耗时 0.04 秒)

    Metal bridging monitor for etch and CMP endpoint detection
    82.
    发明授权
    Metal bridging monitor for etch and CMP endpoint detection 失效
    用于蚀刻和CMP端点检测的金属桥接监视器

    公开(公告)号：US07011762B1

    公开(公告)日：2006-03-14

    申请号：US10419534

    申请日：2003-04-21

    申请人： Christopher F. Lyons ,  Ramkumar Subramanian ,  Steven C. Avanzino

    发明人： Christopher F. Lyons ,  Ramkumar Subramanian ,  Steven C. Avanzino

    IPC分类号： C23F1/00 ,  G01R31/00

    CPC分类号： H01L21/3212 ,  H01L21/32051 ,  H01L21/32136 ,  H01L22/26 ,  H01L2924/0002 ,  H01L2924/00

    摘要： One aspect of the present invention relates to a wafer containing a semiconductor substrate, at least one metal layer formed over the semiconductor substrate, and at least one electrical sensor embedded at least one of on and in the wafer to facilitate real time monitoring of the metal layer as it progresses through a subtractive metallization process. Another aspect of the present relates to a system and method for monitoring a subtractive metallization process in real time in order to effectuate an immediate response in the on-going process. The system contains a wafer comprising at least one metal layer formed on a semiconductor substrate, at least one electrical sensor in contact with the wafer and operable to detect and transmit electrical activity associated with the wafer, and an electrical measurement station operable to process electrical activity detected and received from the electrical sensor for monitoring a subtractive metallization process in real-time.

    摘要翻译： 本发明的一个方面涉及包含半导体衬底的晶片，在半导体衬底上形成的至少一个金属层和至少一个嵌入在晶片内和晶片中的至少一个的电传感器，以便于金属的实时监测 当它通过减色金属化过程进行时。 本发明的另一方面涉及一种用于实时监测减色金属化过程以便在持续过程中实现立即响应的系统和方法。 该系统包含晶片，该晶片包括形成在半导体衬底上的至少一个金属层，与晶片接触的至少一个电传感器，其可操作以检测和传输与晶片相关的电活动;以及电测量站，可操作以处理电活动 从电传感器检测和接收，用于实时监测减色金属化处理。

    Selective stress-inducing implant and resulting pattern distortion in amorphous carbon patterning
    85.
    发明授权
    Selective stress-inducing implant and resulting pattern distortion in amorphous carbon patterning 失效
    选择性应力诱导植入物和无定形碳图案化导致的图案变形

    公开(公告)号：US06825114B1

    公开(公告)日：2004-11-30

    申请号：US10424675

    申请日：2003-04-28

    申请人： Philip A. Fisher ,  Christopher F. Lyons ,  Srikanteswara Dakshina-Murthy

    发明人： Philip A. Fisher ,  Christopher F. Lyons ,  Srikanteswara Dakshina-Murthy

    IPC分类号： H01L2144

    CPC分类号： H01L21/0332 ,  H01L21/32139 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming a fuse for use in an integrated circuit using an amorphous carbon mask includes providing a mask material layer comprising amorphous carbon over a conductive layer. The mask material layer is doped with nitrogen, and an anti-reflective coating (ARC) feature is formed over the mask layer. A portion of the mask material layer is removed according to the ARC feature to form a mask, and the ARC feature is removed to form a warped mask. The conductive layer is patterned according to the warped mask, the warped mask is removed, and a silicide layer is provided over the patterned conductive layer.

    摘要翻译： 使用非晶碳掩模形成用于集成电路的熔丝的方法包括在导电层上提供包含无定形碳的掩模材料层。 掩模材料层掺杂有氮，并且在掩模层上形成抗反射涂层（ARC）特征。 根据ARC特征去除掩模材料层的一部分以形成掩模，并且去除ARC特征以形成翘曲的掩模。 根据翘曲的掩模对导电层进行图案化，去除翘曲的掩模，并且在图案化的导电层上提供硅化物层。

    Dual bake for BARC fill without voids
    88.
    发明授权
    Dual bake for BARC fill without voids 失效
    双烘烤BARC填充无空隙

    公开(公告)号：US06605546B1

    公开(公告)日：2003-08-12

    申请号：US09901699

    申请日：2001-07-11

    申请人： Ramkumar Subramanian ,  Wolfram Grundke ,  Bhanwar Singh ,  Christopher F. Lyons ,  Marina V. Plat

    发明人： Ramkumar Subramanian ,  Wolfram Grundke ,  Bhanwar Singh ,  Christopher F. Lyons ,  Marina V. Plat

    IPC分类号： H01L21302

    CPC分类号： H01L21/76808

    摘要： A method for forming a semiconductor device comprises forming a first layer over a semiconductor substrate. At least one hole is formed through the first layer. A bottom anti-reflective coating (BARC) layer is formed in the at least one hole. A first heating is performed to heat the BARC layer to a flow temperature. A second heating is performed to heat the BARC layer to a hardening temperature so that the BARC layer hardens, wherein the hardening temperature is greater than the flow temperature. An etch is performed to form a trench in the first layer and over the at least one hole, wherein the hardened BARC layer in the at least one hole acts as an etch resistant layer during the etch. As an alternative to the second heating step, the BARC may be simply hardened. The first and second heating may be performed within a heating chamber without removing the semiconductor substrate.

    摘要翻译： 一种用于形成半导体器件的方法包括在半导体衬底上形成第一层。 通过第一层形成至少一个孔。 在至少一个孔中形成底部抗反射涂层（BARC）层。 执行第一次加热以将BARC层加热至流动温度。 执行第二次加热以将BARC层加热至硬化温度，使得BARC层硬化，其中硬化温度大于流动温度。 进行蚀刻以在第一层中和在至少一个孔上形成沟槽，其中至少一个孔中的硬化的BARC层在蚀刻期间用作耐蚀刻层。 作为第二加热步骤的替代方案，BARC可以简单地硬化。 第一和第二加热可以在加热室内进行，而不去除半导体衬底。

    Dual inlaid process using an imaging layer to protect via from poisoning
    89.
    发明授权
    Dual inlaid process using an imaging layer to protect via from poisoning 有权
    双镶嵌工艺使用成像层保护通孔免受中毒

    公开(公告)号：US06458691B1

    公开(公告)日：2002-10-01

    申请号：US09824662

    申请日：2001-04-04

    申请人： Ramkumar Subramanian ,  Christopher F. Lyons ,  Marina V. Plat ,  Bhanwar Singh

    发明人： Ramkumar Subramanian ,  Christopher F. Lyons ,  Marina V. Plat ,  Bhanwar Singh

    IPC分类号： H01L214763

    CPC分类号： H01L21/31144 ,  H01L21/76807

    摘要： There is provided a method of making a dual inlaid via in a first layer. The first layer may be a polymer intermetal dielectric, such as HSQ, of a semiconductor device. The method includes forming a first opening, such as a via, in the first layer and forming an inorganic base radiation sensitive layer in the first opening. The radiation sensitive layer may be a polysilane imaging layer. The inorganic base radiation sensitive layer is selectively exposed to radiation and then patterned. A second opening, such a trench, is formed in communication with the first opening using the patterned inorganic base radiation sensitive layer as a mask. A conductive layer may be formed in the dual inlaid via to complete a dual damascene process.

    摘要翻译： 提供了在第一层中制作双重嵌入通孔的方法。 第一层可以是半导体器件的聚合物金属间电介质，例如HSQ。 该方法包括在第一层中形成诸如通孔的第一开口，并在第一开口中形成无机碱辐射敏感层。 辐射敏感层可以是聚硅烷成像层。 无机碱辐射敏感层选择性地暴露于辐射，然后图案化。 使用图案化的无机基底辐射敏感层作为掩模，形成与第一开口连通的第二开口，这样的沟槽。 可以在双镶嵌通孔中形成导电层以完成双镶嵌工艺。

    T-gate formation using a modified conventional poly process
    90.
    发明授权
    T-gate formation using a modified conventional poly process 有权
    使用改进的常规聚合方法形成T形栅

    公开(公告)号：US06417084B1

    公开(公告)日：2002-07-09

    申请号：US09620300

    申请日：2000-07-20

    申请人： Bhanwar Singh ,  Marina Plat ,  Ramkumar Subramanian ,  Christopher F. Lyons

    发明人： Bhanwar Singh ,  Marina Plat ,  Ramkumar Subramanian ,  Christopher F. Lyons

    IPC分类号： H01L213205

    CPC分类号： H01L21/28114 ,  H01L21/32139

    摘要： A method is provided for fabricating a T-gate structure. A structure is provided that has a silicon layer having a gate oxide layer, a polysilicon layer over the gate oxide layer, and an ARC layer over the polysilicon layer. A gate structure is formed by removing the ARC layer and a portion of the polysilicon layer around a gate region. Spacers are then formed around the gate structure. Undercut regions are formed in the gate structure by performing an isotropic etch to provide the gate structure with a base region and a contact region. The base region has a width smaller than the contact region.

    摘要翻译： 提供了一种用于制造T型栅结构的方法。 提供一种结构，其具有硅层，该硅层具有栅极氧化物层，栅极氧化物层上的多晶硅层以及多晶硅层上的ARC层。 通过在栅极区域周围除去ARC层和多晶硅层的一部分来形成栅极结构。 然后在栅极结构周围形成间隔物。 通过执行各向同性蚀刻在栅极结构中形成底切区域，以向栅极结构提供基极区域和接触区域。 基部区域的宽度小于接触区域。