公开(公告)号：US06621750B2

公开(公告)日：2003-09-16

申请号：US10155029

申请日：2002-05-28

申请人： Yoshiaki Okuyama ,  Shinya Fujioka ,  Kota Hara ,  Katsuhiro Mori

发明人： Yoshiaki Okuyama ,  Shinya Fujioka ,  Kota Hara ,  Katsuhiro Mori

IPC分类号： G11C700

CPC分类号： G11C29/808 ,  G11C29/812 ,  G11C29/848

摘要： A redundancy memory circuit stores a defect address indicating a defective memory cell row. A redundancy control circuit disables the defective memory cell row corresponding to the defect address stored in the redundancy memory circuit and enables a redundancy memory cell row in the memory block containing the defective memory cell row. Moreover, in the other memory blocks, the redundancy control circuit disables memory cell rows corresponding to the defective memory cell row and enables redundancy memory cell rows instead of these memory cell rows. Consequently, not only the memory block having the defective memory cell row but one of the memory cell rows in the other memory blocks is always also relieved. Thus, the redundancy memory circuit can be shared among all the memory blocks with a reduction in the number of redundancy memory circuits. As a result, the semiconductor memory can be reduced in chip size.

公开(公告)号：US06584032B2

公开(公告)日：2003-06-24

申请号：US09949847

申请日：2001-09-12

申请人： Shinya Fujioka ,  Tomohiro Kawakubo ,  Koichi Nishimura ,  Kotoku Sato

发明人： Shinya Fujioka ,  Tomohiro Kawakubo ,  Koichi Nishimura ,  Kotoku Sato

IPC分类号： G11C700

CPC分类号： G06F1/3234 ,  G06F1/3203 ,  G06F1/3268 ,  G06F1/3275 ,  G11C5/14 ,  G11C5/145 ,  G11C5/147 ,  G11C11/406 ,  G11C11/40615 ,  G11C14/00 ,  G11C2207/2227 ,  G11C2211/4067 ,  H02M3/07 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

摘要： An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

摘要翻译： 内部电压发生器激活时，产生内部电压供给内部电路。 操作内部电压发生器消耗预定量的功率。 响应来自外部的控制信号，入口电路使内部电压发生器失活。 内部电压发生器未激活时，不产生内部电压，从而降低功耗。 因此，通过来自外部的控制信号，芯片可以容易地进入低功耗模式。 内部电压发生器的例子是用于产生与存储器单元连接的字线的升压电压的升压器，用于产生衬底电压的衬底电压发生器或用于产生要连接的位线的预充电电压的预充电电压发生器 记忆细胞。

公开(公告)号：US06566937B1

公开(公告)日：2003-05-20

申请号：US10152579

申请日：2002-05-23

申请人： Katsuhiro Mori ,  Shinya Fujioka ,  Masahiro Niimi

发明人： Katsuhiro Mori ,  Shinya Fujioka ,  Masahiro Niimi

IPC分类号： H01H3776

CPC分类号： G11C17/16

摘要： Upon receiving a level of a second node through a third switch in the first half of a first period, a holding circuit outputs it as a fuse signal indicating a blown-out state of a fuse. Since the third switch turns off in the second half of the first period, a change in level of the second node occurring thereafter will not affect data in the holding circuit, whereby prevents malfunction of a fuse circuit. With the fuse blown, a level of a first node gets fixed at that of a second power supply line after the first period. This eliminates a voltage difference between both ends of the fuse, thereby preventing a growback. No occurrence of growback makes just one fuse blowing sufficient for the fuse circuit even with the fuse not completely cut off. This consequently shortens a time for blowing the fuse in a test process.

摘要翻译： 在第一周期的前半段通过第三开关接收到第二节点的电平时，保持电路将其作为指示保险丝的熔断状态的熔丝信号输出。 由于在第一周期的后半部分中第三开关断开，所以其后发生的第二节点的电平变化不会影响保持电路中的数据，从而防止熔丝电路的故障。 在保险丝熔断时，在第一周期之后，第一节点的电平固定在第二电源线的电平上。 这消除了保险丝两端之间的电压差，从而防止了长时间的恢复。 即使没有完全切断保险丝，也不会发生长时间退回，只有一个保险丝对保险丝电路充足。 从而缩短了在测试过程中熔断熔断器的时间。

公开(公告)号：US06563746B2

公开(公告)日：2003-05-13

申请号：US09820795

申请日：2001-03-30

申请人： Shinya Fujioka ,  Tomohiro Kawakubo ,  Koichi Nishimura ,  Kotoku Sato

发明人： Shinya Fujioka ,  Tomohiro Kawakubo ,  Koichi Nishimura ,  Kotoku Sato

IPC分类号： G11C700

CPC分类号： G06F1/3234 ,  G06F1/3203 ,  G06F1/3268 ,  G06F1/3275 ,  G11C5/14 ,  G11C5/145 ,  G11C5/147 ,  G11C11/406 ,  G11C11/40615 ,  G11C14/00 ,  G11C2207/2227 ,  G11C2211/4067 ,  H02M3/07 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

摘要： An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

摘要翻译： 内部电压发生器激活时，产生内部电压供给内部电路。 操作内部电压发生器消耗预定量的功率。 响应来自外部的控制信号，入口电路使内部电压发生器失活。 内部电压发生器未激活时，不产生内部电压，从而降低功耗。 因此，通过来自外部的控制信号，芯片可以容易地进入低功耗模式。 内部电压发生器的例子是用于产生与存储器单元连接的字线的升压电压的升压器，用于产生衬底电压的衬底电压发生器或用于产生要连接的位线的预充电电压的预充电电压发生器 记忆细胞。

公开(公告)号：US06373764B1

公开(公告)日：2002-04-16

申请号：US09790573

申请日：2001-02-23

申请人： Shinya Fujioka

发明人： Shinya Fujioka

IPC分类号： G11C700

摘要： A semiconductor memory device includes bit lines which transfer data of memory cells, a plurality of first sense amplifier circuits connected to odd-number lines of the bit lines, a plurality of second sense amplifier circuits connected to even-number lines of the bit lines, and a clamp-voltage generation circuit which supplies a first clamp voltage to the first sense amplifier circuits, and supplies a second clamp voltage to the second sense amplifier circuits, whereby during test operation, the odd-number lines are clamped to the first clamp voltage, and the even-number lines are clamped to the second clamp voltage.

公开(公告)号：US06341100B1

公开(公告)日：2002-01-22

申请号：US09575363

申请日：2000-05-22

申请人： Shinya Fujioka

发明人： Shinya Fujioka

IPC分类号： G11C800

CPC分类号： G11C11/4076 ,  G11C7/1006 ,  G11C7/1072 ,  G11C11/4096 ,  G11C2207/229

摘要： A controlling signal generating unit generates a bit line controlling signal, a word line signal, a sense amplifier activating signal, and a column line signal. The bit line controlling signal activates a resetting circuit which resets a bit line. The word line signal controls the connection between a memory cell and the bit line which transmits data to the memory cell. The sense amplifier activating signal activates a sense amplifier which amplifies data transmitted to the bit line. The column line signal activates a column switch which transmits data to the bit line. The controlling signal generating unit activates predetermined signal(s) among the word line signal, the sense amplifier activating signal, the bit line controlling signal, and the column line signal at the start of a write operation. The controlling signal generating unit activates the remaining signal(s) after the acceptance of write data. Since the predetermined signal(s) is/are activated without the acceptance of write data, it is possible to make the activating timing of the remaining signal(s) earlier. This consequently reduces the time necessary for a write operation.

摘要翻译： 控制信号产生单元产生位线控制信号，字线信号，读出放大器激活信号和列线信号。 位线控制信号激活复位位线的复位电路。 字线信号控制存储单元与向存储单元发送数据的位线之间的连接。 读出放大器激活信号激活读出放大器，其放大发送到位线的数据。 列线信号激活向位线发送数据的列开关。 控制信号产生单元在写入操作开始时激活字线信号，读出放大器激活信号，位线控制信号和列线信号之间的预定信号。 控制信号产生单元在接受写入数据之后激活剩余的信号。 由于在不接受写入数据的情况下激活预定信号，所以可以使剩余信号的激活定时更早。 这因此减少了写操作所需的时间。

公开(公告)号：US06301173B2

公开(公告)日：2001-10-09

申请号：US09307758

申请日：1999-05-10

申请人： Shinya Fujioka ,  Yasuharu Sato

发明人： Shinya Fujioka ,  Yasuharu Sato

IPC分类号： G11C700

CPC分类号： G11C7/065 ,  G11C7/12

摘要： The present invention is a memory circuit having a plurality of word lines, a plurality of bit line pairs, and memory cells disposed at the cross-position thereof. The memory comprises: a sense amplifier which is shared by the first bit line pair and the second bit line pair disposed in the column direction and amplifies a voltage of the bit line pairs; a first and a second bit line transfer gates which are disposed between the sense amplifier and the first and second bit line pairs, and connects the bit line pair at the selected memory cell side to the sense amplifier; a bit line clamper, which is disposed between the first and second bit line transfer gates, is shared by the first bit line pair and the second bit line pair, and supplies the precharge level to the bit line pairs; and a bit line short circuit, which is disposed at the first and the second bit line pairs respectively and shorts the bit line pairs. According to the above structure, the reset operation involving a bit line short operation can be executed at high-speed, since the bit line short circuit is disposed for each bit line pair. Also area efficiency can be improved since the bit line clamper circuit is shared by the first and the second bit line pairs.

摘要翻译： 本发明是具有多个字线，多个位线对和设置在其交叉位置的存储单元的存储电路。 存储器包括：读出放大器，由第一位线对和位于列方向上的第二位线对共享，并放大位线对的电压; 第一位线传输门和第二位线传输门，其布置在读出放大器与第一和第二位线对之间，并将所选存储单元侧的位线对连接到读出放大器; 位于第一和第二位线传输门之间的位线钳位器由第一位线对和第二位线对共用，并将预充电电平提供给位线对; 以及分别布置在第一和第二位线对上并使位线对短路的位线短路。 根据上述结构，由于对每个位线对设置位线短路，所以可以高速执行涉及位线短路操作的复位动作。 由于位线钳位电路由第一位线对和第二位线对共享，所以可以提高面积效率。

公开(公告)号：US5970019A

公开(公告)日：1999-10-19

申请号：US35101

申请日：1998-03-05

申请人： Takaaki Suzuki ,  Shinya Fujioka

发明人： Takaaki Suzuki ,  Shinya Fujioka

IPC分类号： G11C11/407 ,  G06F12/02 ,  G11C8/14 ,  G11C11/401 ,  G11C8/00

CPC分类号： G11C8/14

摘要： A semiconductor memory device which employs a hierarchical word-decode scheme for word selection includes sub-word lines provided for each of column blocks, a control circuit selecting one of the column blocks corresponding to a currently accessed column address in a first case where a currently accessed row address is different from a successively accessed row address, and selecting all of the column blocks in a second case where the currently accessed row address is the same as the successively accessed row address, and a sub-word decoder selectively activating the sub-word lines with respect to all of one or more column blocks selected by the control circuit.

摘要翻译： 采用用于字选择的分级字解码方案的半导体存储器件包括为每个列块提供的子字线，控制电路在当前访问的列地址中选择与当前访问的列地址相对应的列之一 所访问的行地址不同于连续访问的行地址，并且在当前访问的行地址与连续访问的行地址相同的第二种情况下选择所有列块，并且子字解码器选择性地激活子地址， 相对于由控制电路选择的所有一个或多个列块的字线。

公开(公告)号：US5804893A

公开(公告)日：1998-09-08

申请号：US818714

申请日：1997-03-14

申请人： Shinya Fujioka

发明人： Shinya Fujioka

IPC分类号： G06F1/26 ,  G06F1/32 ,  G11C5/14 ,  G11C11/407 ,  H03K3/027

CPC分类号： G11C5/147 ,  Y10T307/766 ,  Y10T307/826

摘要： A semiconductor device operable in a selected mode which is selected from a plurality of operation modes, a number of the operation modes being more than two. The semiconductor device includes a plurality of voltage supply circuits for supplying an internal voltage to internal circuits of the semiconductor device, and a control circuit for driving a predetermined number of the voltage supply circuits based on a signal indicating the selected mode, the control circuit changing the predetermined number for each of the operation modes.

摘要翻译： 一种半导体器件，其以从多个操作模式中选择的选择模式操作，多个操作模式大于2。 半导体器件包括用于向半导体器件的内部电路提供内部电压的多个电压供给电路和用于基于指示所选择的模式的信号来驱动预定数量的电压供应电路的控制电路，控制电路改变 每个操作模式的预定数量。

公开(公告)号：US08619487B2

公开(公告)日：2013-12-31

申请号：US13356341

申请日：2012-01-23

申请人： Shinya Fujioka ,  Tomohiro Kawakubo ,  Koichi Nishimura ,  Kotoku Sato

发明人： Shinya Fujioka ,  Tomohiro Kawakubo ,  Koichi Nishimura ,  Kotoku Sato

IPC分类号： G11C7/00 ,  G11C5/14

CPC分类号： G06F1/3234 ,  G06F1/3203 ,  G06F1/3268 ,  G06F1/3275 ,  G11C5/14 ,  G11C5/145 ,  G11C5/147 ,  G11C11/406 ,  G11C11/40615 ,  G11C14/00 ,  G11C2207/2227 ,  G11C2211/4067 ,  H02M3/07 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

摘要： A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.

摘要翻译： 半导体器件包括具有多个存储单元的存储器芯，内部电压发生器和低功率入口电路。 低功率入口电路接收提供给命令解码器的多个控制信号，并产生指示禁止刷新操作的低功耗模式的低功率信号。 内部电压发生器包括检测器和至少一个升压电路。 内部电压发生器通过内部电源线耦合到存储器核心，基于外部电压产生升压的内部电压，并通过内部电源线将升压的内部电压提供给存储器核心。 内部电压发生器在向外部电压提供给半导体器件时停止向内部电源线提供升压的内部电压以响应于低功率信号。