公开(公告)号：US07212369B1

公开(公告)日：2007-05-01

申请号：US10920717

申请日：2004-08-16

申请人： Lloyd Levy ,  Yu Sun ,  Pang L. Tan ,  Jingbo Yu ,  Adrian Cerda

发明人： Lloyd Levy ,  Yu Sun ,  Pang L. Tan ,  Jingbo Yu ,  Adrian Cerda

IPC分类号： G11B21/02

CPC分类号： G11B5/59633 ,  G11B5/59638 ,  G11B5/59661 ,  G11B5/59666

摘要： A method and apparatus for providing a temporary utility zone in a disk drive. A disk surface has a write head associated therewith. The write head is used to write spiral servo information and a propagation state indicator onto the disk surface. The spiral servo information and propagation state indicator are used to perform a self-servo write operation on the disk surface.

摘要翻译： 一种用于在磁盘驱动器中提供临时实用区域的方法和装置。 磁盘表面具有与其相关联的写入头。 写头用于将螺旋伺服信息和传播状态指示器写入磁盘表面。 螺旋伺服信息和传播状态指示器用于对盘表面进行自伺服写操作。

公开(公告)号：US07167336B1

公开(公告)日：2007-01-23

申请号：US10410576

申请日：2003-04-08

申请人： Richard M. Ehrlich ,  Don Brunnett ,  Yu Sun

发明人： Richard M. Ehrlich ,  Don Brunnett ,  Yu Sun

IPC分类号： G11B5/596

CPC分类号： G11B5/59627

摘要： A method for determining embedded runout correction (ERC) values using iteration and variable gain in a disk drive. A disk has a track written thereon, an ERC value is determined for a servo sector on the track using variable gain, and the variable gain decreases based on the number of revolutions of the disk.

摘要翻译： 一种使用磁盘驱动器中的迭代和可变增益来确定嵌入式跳动校正（ERC）值的方法。 磁盘具有写入的轨道，使用可变增益确定轨道上的伺服扇区的ERC值，并且可变增益基于盘的转数而减小。

公开(公告)号：US07060564B1

公开(公告)日：2006-06-13

申请号：US10635089

申请日：2003-08-06

申请人： Inkuk Kang ,  Hiroyuki Kinoshita ,  Weidong Qian ,  Kelwin King Wai Ko ,  Yu Sun

发明人： Inkuk Kang ,  Hiroyuki Kinoshita ,  Weidong Qian ,  Kelwin King Wai Ko ,  Yu Sun

IPC分类号： H01L21/336

CPC分类号： H01L27/105 ,  H01L27/11568 ,  H01L27/11573

摘要： A method of fabricating a memory device having a core region of double-bit memory cells and a periphery region of logic circuitry includes forming a dielectric stack over the core and periphery areas of a semiconductor substrate and removing the dielectric stack from the periphery region. A gate dielectric is formed over the periphery area, followed by a first conductive layer over the core and periphery areas. After the formation and thermal processing of the gate dielectric, bitlines, which serve as source and drain regions, are implanted into the core area. Formation of the bitlines after the gate dielectric layer reduces lateral bitline diffusion and reduces short channel effects.

摘要翻译： 一种制造具有双位存储器单元的核心区域和逻辑电路的外围区域的存储器件的方法包括在半导体衬底的芯部和外围区域上形成电介质堆叠并从外围区域去除电介质堆叠。 在外围区域上形成栅极电介质，随后在芯部和外围区域上形成第一导电层。 在栅极电介质的形成和热处理之后，用作源极和漏极区的位线被植入核心区域。 栅介质层之后的位线形成减少了横向位线扩散并减少了短沟道效应。

公开(公告)号：US07054096B1

公开(公告)日：2006-05-30

申请号：US10338047

申请日：2003-01-06

申请人： Yu Sun ,  Lin Guo ,  Don Brunnett

发明人： Yu Sun ,  Lin Guo ,  Don Brunnett

IPC分类号： G11B5/596

CPC分类号： G11B5/59627 ,  G11B5/59633 ,  G11B5/59666

摘要： A method and apparatus for compensating for non-linearities due to pivot bearing friction when determining embedded runout correction values during partial self-servo write of a disk drive is disclosed. In one embodiment, the disk drive includes a disk surface having a track written thereon and the track has some written-in runout. The written-in runout that is associated with high-frequencies is determined using a first technique. The written-in runout for the track that is associated with low frequencies is determined using a second technique. Results from the two techniques are combined in order to determine embedded runout correction values for the track when partial self-servo writing, in order to reduce error propagation when writing additional tracks.

摘要翻译： 公开了一种在磁盘驱动器的部分自伺服写入期间确定嵌入的跳动校正值时补偿由于枢转轴承摩擦导致的非线性的方法和装置。 在一个实施例中，盘驱动器包括具有写在其上的轨道的盘表面，并且轨道具有一些写入的跳动。 使用第一技术确定与高频相关联的写入跳动。 使用第二种技术确定与低频相关的轨道的写入跳动。 组合两种技术的结果，以便在部分自伺服写入时确定轨道的嵌入式跳动校正值，以便在写入附加轨道时减少误差传播。

公开(公告)号：US07027253B1

公开(公告)日：2006-04-11

申请号：US11050118

申请日：2005-02-03

申请人： Yu Sun ,  Yunfeng Li ,  Lin Guo

发明人： Yu Sun ,  Yunfeng Li ,  Lin Guo

IPC分类号： G11B21/02 ,  G11B5/596

CPC分类号： G11B5/59633 ,  G11B5/5552 ,  G11B5/59666 ,  G11B5/59694

摘要： Compensation for disk mode disturbances during self-writing of servo data is provided in a manner that accounts for differences in orientation between the disk surface from which position information is derived and the disk surface on which servo data is written. Microactuators corresponding to upper surfaces of disks may have a wiring polarity that is out of phase with the wiring polarity of microactuators corresponding to upper surfaces of disks so that disk mode compensation signals supplied to the microactuators produce motion in opposite directions. The servo control system may supply signals to microactuators individually and select the polarities of those signals to account for differences in orientation between the disk surface from which position information is derived and the disk surface on which servo data is written.

摘要翻译： 提供伺服数据自写入期间的磁盘模式干扰的补偿，其方式是考虑到导出位置信息的磁盘表面与写入伺服数据的磁盘表面之间的方向上的差异。 对应于盘的上表面的微致动器可以具有与对应于盘的上表面的微致动器的布线极性相异的布线极性，使得提供给微致动器的盘模补偿信号产生相反方向的运动。 伺服控制系统可以单独向微型致动器提供信号，并选择这些信号的极性，以解决导出位置信息的磁盘表面与写入伺服数据的磁盘表面之间的方向上的差异。

公开(公告)号：US07012780B1

公开(公告)日：2006-03-14

申请号：US11070783

申请日：2005-03-02

申请人： Xiaoping Hu ,  Yu Sun ,  Lin Guo ,  Donald Brunett

发明人： Xiaoping Hu ,  Yu Sun ,  Lin Guo ,  Donald Brunett

IPC分类号： G11B5/596

CPC分类号： G11B5/5552 ,  G11B5/4886

摘要： A disk drive includes a data storage disk, a transducer, a micro actuator, a coarse actuator, and a controller. The micro actuator is configured to position the transducer relative to the disk over a first range of movement. The coarse actuator is configured to position the micro actuator relative to the disk over a second range of movement that is larger than the first range of movement. The controller is configured to control positioning of the transducer by the coarse actuator and the micro actuator in a track following operation, and in a seek operation responsive to a seek command. The controller is also configured to calibrate its positioning of the transducer by the micro actuator responsive to receipt of the seek command and prior to seeking the transducer from an initial track to a target track.

摘要翻译： 磁盘驱动器包括数据存储盘，换能器，微执行器，粗执行器和控制器。 微致动器构造成在第一移动范围上相对于盘定位换能器。 粗致动器被构造成在比第一移动范围大的第二移动范围内相对于盘定位微致动器。 控制器被配置为通过粗略致动器和微型致动器在跟踪操作中控制换能器的定位，以及响应于寻道命令的寻道操作。 控制器还被配置为响应于接收到寻道命令并且在从初始轨迹到目标轨道寻找换能器之前，通过微执行器校准其换能器的定位。

公开(公告)号：US06989319B1

公开(公告)日：2006-01-24

申请号：US10718707

申请日：2003-11-24

申请人： Mark Ramsbey ,  Sameer Haddad ,  Vei-Han Chan ,  Yu Sun ,  Chi Chang

发明人： Mark Ramsbey ,  Sameer Haddad ,  Vei-Han Chan ,  Yu Sun ,  Chi Chang

IPC分类号： H01L21/265

CPC分类号： H01L21/265 ,  H01L21/28176 ,  H01L21/28273

摘要： Methods and arrangements are provided for significantly reducing electron trapping in semiconductor devices having a polysilicon feature and an overlying dielectric layer. The methods and arrangements employ a nitrogen-rich region within the polysilicon feature near the interface to the overlying dielectric layer. The methods include selectively implanting nitrogen ions through at least a portion of the overlying dielectric layer and into the polysilicon feature to form an initial nitrogen concentration profile within the polysilicon feature. Next, the temperature within the polysilicon feature is raised to an adequately high temperature, for example using rapid thermal anneal (RTA) techniques, which cause the initial nitrogen concentration profile to change due to the migration of the majority of the nitrogen towards either the interface with the overlying dielectric layer or the interface with an underlying layer. Consequently, the polysilicon feature has a first nitrogen-rich region near the interface to the overlying dielectric layer and a second nitrogen-rich region near the interface to the underlying layer. The migration of nitrogen further forms a contiguous reduced-nitrogen region located between the first nitrogen-rich region and the second nitrogen-rich region. The contiguous reduced-nitrogen region has a lower concentration of nitrogen than does the first nitrogen-rich region and the second nitrogen-rich region. The first nitrogen-rich region has been found to reduce electron trapping within the polysilicon feature. Thus, for example, in a non-volatile memory device wherein the polysilicon feature is a floating gate, false programming of the memory device can be significantly avoided by reducing the number of trapped electrons in the floating gate.

摘要翻译： 提供了用于显着减少具有多晶硅特征和上覆电介质层的半导体器件中的电子俘获的方法和装置。 所述方法和装置在靠近覆盖的介电层的界面附近使用多晶硅特征内的富氮区域。 所述方法包括通过至少部分上覆介质层选择性地注入氮离子并进入多晶硅特征以在多晶硅特征内形成初始氮浓度分布。 接下来，将多晶硅特征中的温度升高到足够高的温度，例如使用快速热退火（RTA）技术，其使得初始氮浓度分布由于大部分氮朝着界面迁移而改变 与上层电介质层或与下层的界面。 因此，多晶硅特征具有在与上覆电介质层的界面附近的第一富氮区域和与下层的界面附近的第二富氮区域。 氮的迁移进一步形成位于第一富氮区和第二富氮区之间的连续的还原氮区。 连续的还原氮区域具有比第一富氮区域和第二富氮区域低的氮浓度。 已发现第一富氮区域减少多晶硅特征内的电子俘获。 因此，例如，在其中多晶硅特征是浮动栅极的非易失性存储器件中，可以通过减少浮置栅极中的俘获电子的数量来显着地避免存储器件的伪编程。

公开(公告)号：US20050164450A1

公开(公告)日：2005-07-28

申请号：US10762445

申请日：2004-01-22

申请人： Shenqing Fang ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Richard Fastow ,  Angela Hui ,  Kazuhiro Mizutani ,  Kelwin Ko ,  Hiroyuki Kinoshita ,  Yu Sun ,  Hiroyuki Ogawa

发明人： Shenqing Fang ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Richard Fastow ,  Angela Hui ,  Kazuhiro Mizutani ,  Kelwin Ko ,  Hiroyuki Kinoshita ,  Yu Sun ,  Hiroyuki Ogawa

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/74 ,  H01L29/417 ,  H01L29/788

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L21/743 ,  H01L29/41766 ,  H01L29/66636

摘要： According to one exemplary embodiment, a floating gate memory cell comprises a stacked gate structure situated on a substrate and situated over a channel region in the substrate. The floating gate memory cell further comprises a recess formed in the substrate adjacent to the stacked gate structure, where the recess has a sidewall, a bottom, and a depth. According to this exemplary embodiment, the floating gate memory cell further comprises a source situated adjacent to the sidewall of the recess and under the stacked gate structure. The floating gate memory cell further comprises a Vss connection region situated under the bottom of the recess and under the source, where the Vss connection region is connected to the source. The Vss connection region being situated under the bottom of the recess causes the source to have a reduced lateral diffusion in the channel region.

摘要翻译： 根据一个示例性实施例，浮动栅极存储器单元包括位于衬底上并位于衬底中的沟道区域上方的堆叠栅极结构。 浮动栅极存储单元还包括形成在衬底中的与堆叠的栅极结构相邻的凹部，其中凹部具有侧壁，底部和深度。 根据该示例性实施例，浮动栅极存储单元还包括位于与凹部的侧壁相邻并位于堆叠栅极结构下方的源极。 浮动栅极存储单元还包括位于凹部底部下方和源极之下的Vss连接区域，其中Vss连接区域连接到源极。 位于凹部底部下方的Vss连接区使得源在通道区域中具有减小的横向扩散。

公开(公告)号：US06808992B1

公开(公告)日：2004-10-26

申请号：US10150240

申请日：2002-05-15

申请人： Kelwin Ko ,  Shenqing Fang ,  Angela T. Hui ,  Hiroyuki Kinoshita ,  Wenmei Li ,  Yu Sun ,  Hiroyuki Ogawa

发明人： Kelwin Ko ,  Shenqing Fang ,  Angela T. Hui ,  Hiroyuki Kinoshita ,  Wenmei Li ,  Yu Sun ,  Hiroyuki Ogawa

IPC分类号： H01L21336

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11536 ,  H01L29/6656

摘要： A method and system for providing a semiconductor device are described. The semiconductor device includes a substrate, a core and a periphery. The core includes a plurality of core gate stacks having a first plurality of edges, while the periphery a plurality of periphery gate stacks having a second plurality of edges. The method and system include providing a plurality of core spacers, a plurality of periphery spacers, a plurality of core sources and a plurality of conductive regions. The core spacers reside at the first plurality of edges and have a thickness. The periphery spacers reside at the second plurality of edges and have a second thickness greater than the first thickness. The core sources reside between the plurality of core gate stacks. The conductive regions are on the plurality of core sources. This method allows different thicknesses of the spacers to be formed in the core and the periphery so that the spacers can be tailored to the different requirements of the core and periphery.

摘要翻译： 描述了一种用于提供半导体器件的方法和系统。 半导体器件包括衬底，芯和周边。 芯包括具有第一多个边缘的多个核心栅极叠层，而周边具有多个具有第二多个边缘的外围栅极堆叠。 该方法和系统包括提供多个芯间隔件，多个外围间隔件，多个芯源和多个导电区域。 芯间隔件位于第一多个边缘处并且具有厚度。 外围间隔件位于第二多个边缘处并且具有大于第一厚度的第二厚度。 核心源位于多个核心门堆栈之间。 导电区域在多个核心源上。 该方法允许不同厚度的间隔件形成在芯部和周边中，使得间隔件可以根据芯部和周边的不同要求进行调整。

公开(公告)号：US06780708B1

公开(公告)日：2004-08-24

申请号：US10382744

申请日：2003-03-05

申请人： Hiroyuki Kinoshita ,  Yu Sun ,  Basab Banerjee ,  Christopher M. Foster ,  John R. Behnke ,  Cyrus Tabery

发明人： Hiroyuki Kinoshita ,  Yu Sun ,  Basab Banerjee ,  Christopher M. Foster ,  John R. Behnke ,  Cyrus Tabery

IPC分类号： H01L218242

CPC分类号： H01L27/105 ,  H01L27/11568 ,  H01L27/11573

摘要： A method for forming a semiconductor device that includes a line and space pattern with variable pitch and critical dimensions in a layer on a substrate. The substrate includes a first region (e.g., a core region) and a second region (e.g., a periphery region). A first sub-line and space pattern in the first region comprises a space of a dimension (A) less than achievable by lithographic processes alone. Further, a second sub-line and space pattern in the second region comprises at least one line including a second critical dimension (B) achievable by lithography. The method uses two critical masking steps to form a hard mask that includes in the core region a critical dimension (A) less than achievable at a resolution limit of lithography. Further, the method uses a single etch step to transfer the pattern of the hard mask to the layer.

摘要翻译： 一种用于形成半导体器件的方法，其包括在衬底上的层中具有可变节距和临界尺寸的线和间隔图案。 衬底包括第一区域（例如芯区域）和第二区域（例如，周边区域）。 第一区域中的第一子线和空间图案包括尺寸（A）的空间小于单独通过光刻工艺可实现的尺寸。 此外，第二区域中的第二子线和空间图案包括至少一条线，其包括通过光刻可实现的第二临界尺寸（B）。 该方法使用两个关键的掩模步骤来形成硬掩模，其在芯部区域中包括小于在光刻的分辨率极限下可实现的临界尺寸（A）。 此外，该方法使用单个蚀刻步骤将硬掩模的图案转移到该层。