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    HEAT INSULATING INTERCONNECT FEATURES IN A COMPONENT OF A COMPOSITE IC DEVICE STRUCTURE
    81.
    发明申请
    HEAT INSULATING INTERCONNECT FEATURES IN A COMPONENT OF A COMPOSITE IC DEVICE STRUCTURE 有权

    公开(公告)号：US20220415853A1

    公开(公告)日：2022-12-29

    申请号：US17358948

    申请日：2021-06-25

    Applicant: Intel Corporation

    Inventor： Aleksandar Aleksov ,  Johanna Swan ,  Shawna Liff ,  Feras Eid ,  Adel Elsherbini ,  Julien Sebot

    IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

    Abstract: A composite integrated circuit (IC) structure includes at least a first IC die in a stack with a second IC die. Each die has a device layer and metallization layers interconnected to transistors of the device layer and terminating at features. First features of the first IC die are primarily of a first composition with a first microstructure. Second features of the second IC die are primarily of a second composition or a second microstructure. A first one of the second features is in direct contact with one of the first features. The second composition has a thermal conductivity at least an order of magnitude lower than that of the first composition and first microstructure. The first composition may have a thermal conductivity at least 40 times that of the second composition or second microstructure.

    COMPOSITE INTERPOSER STRUCTURE AND METHOD OF PROVIDING SAME
    83.
    发明申请
    COMPOSITE INTERPOSER STRUCTURE AND METHOD OF PROVIDING SAME 有权

    公开(公告)号：US20220084949A1

    公开(公告)日：2022-03-17

    申请号：US17536804

    申请日：2021-11-29

    Applicant: INTEL CORPORATION

    Inventor： Adel Elsherbini ,  Shawna Liff ,  Johanna Swan ,  Gerald Pasdast

    IPC: H01L23/538 ,  H01L21/304 ,  H01L21/48 ,  H01L23/00

    Abstract: Techniques and mechanisms for high interconnect density communication with an interposer. In some embodiments, an interposer comprises a substrate and portions disposed thereon, wherein respective inorganic dielectrics of said portions adjoin each other at a material interface, which extends to each of the substrate and a first side of the interposer. A first hardware interface of the interposer spans the material interface at the first side, wherein a first one of said portions comprises first interconnects which couple the first hardware interface to a second hardware interface at the first side. A second one of said portions includes second interconnects which couple one of first hardware interface or the second hardware interface to a third hardware interface at another side of the interposer. In another embodiment, a metallization pitch feature of the first hardware interface is smaller than a corresponding metallization pitch feature of the second hardware interface.

    Thermal management solutions for stacked integrated circuit devices using unidirectional heat transfer devices
    84.
    发明授权
    Thermal management solutions for stacked integrated circuit devices using unidirectional heat transfer devices 有权

    公开(公告)号：US11234343B2

    公开(公告)日：2022-01-25

    申请号：US15970420

    申请日：2018-05-03

    Applicant: Intel Corporation

    Inventor： Feras Eid ,  Adel Elsherbini ,  Johanna Swan

    IPC: H05K7/20 ,  H01L25/065 ,  H01L23/427 ,  H01L23/367 ,  H01L23/00

    Abstract: An integrated circuit structure may be formed having a first integrated circuit device, a second integrated circuit device electrically coupled to the first integrated circuit device, and at least one unidirectional heat transfer device between the first integrated circuit device and the second integrated circuit device. In one embodiment, the unidirectional heat transfer device may be oriented such that it has a higher conductivity in the direction of heat transfer from the first integrated circuit device to the second integrated circuit device than it does in the opposite direction. When the temperature of the second integrated circuit device rises above the temperature of the first integrated circuit device, the unidirectional heat transfer device will act as a thermal insulator, and when the temperature of the first integrated circuit device rises above the temperature of the second integrated circuit device, the unidirectional heat transfer device will act as a thermal conductor.

    Selective recess of interconnects for probing hybrid bond devices
    88.
    发明授权
    Selective recess of interconnects for probing hybrid bond devices 有权

    公开(公告)号：US11189585B2

    公开(公告)日：2021-11-30

    申请号：US16703298

    申请日：2019-12-04

    Applicant: Intel Corporation

    Inventor： Brennen K. Mueller ,  Adel Elsherbini ,  Mauro Kobrinsky ,  Johanna Swan ,  Shawna Liff ,  Pooya Tadayon

    IPC: H01L23/52 ,  H01L23/00

    Abstract: An Integrated Circuit (IC) device comprising a first component, the first component comprising a first dielectric and a plurality of adjacent first interconnect structures within the first dielectric. The IC device comprising a second component, the second component comprising a second dielectric and a plurality of adjacent second interconnect structures within the second dielectric. A first of the second interconnect structures is in direct contact with a first of the first interconnect structures at a bond interface between the first and second components. A second of the first interconnect structures is set back a distance from a plane of the bond interface.

    INTERCONNECTION STRUCTURE FABRICATION USING GRAYSCALE LITHOGRAPHY
    89.
    发明申请
    INTERCONNECTION STRUCTURE FABRICATION USING GRAYSCALE LITHOGRAPHY 有权

    公开(公告)号：US20210343635A1

    公开(公告)日：2021-11-04

    申请号：US17375360

    申请日：2021-07-14

    Applicant: Intel Corporation

    Inventor： Johanna Swan ,  Henning Braunisch ,  Aleksandar Aleksov ,  Shawna Liff ,  Brandon Rawlings ,  Veronica Strong

    IPC: H01L23/498 ,  G03F1/38 ,  G03F1/54 ,  G03F1/68

    Abstract: An lithographic reticle may be formed comprising a transparent substrate, a substantially opaque mask formed on the transparent substrate that defines at least one exposure window, wherein the at least one exposure window has a first end, a first filter formed on the transparent substrate within the at least one exposure window and abutting the first end thereof, and a second filter formed on the transparent substrate within the at least one exposure window and abutting the first filter, wherein an average transmissivity of the first filter is substantially one half of a transmissivity of the second filter. In another embodiment, the at least one exposure window includes a third filter abutting the second end and is adjacent the second filter. Further embodiments of the present description include interconnection structures and systems fabricated using the lithographic reticle.

    Composite IC chips including a chiplet embedded within metallization layers of a host IC chip
    90.
    发明授权
    Composite IC chips including a chiplet embedded within metallization layers of a host IC chip 有权

    公开(公告)号：US11094672B2

    公开(公告)日：2021-08-17

    申请号：US16586145

    申请日：2019-09-27

    Applicant: Intel Corporation

    Inventor： Adel Elsherbini ,  Johanna Swan ,  Shawna Liff ,  Patrick Morrow ,  Gerald Pasdast ,  Van Le

    IPC: H01L25/065 ,  H01L23/538 ,  H01L23/522 ,  H01L23/00 ,  H01L25/00

    Abstract: Composite IC chip including a chiplet embedded within metallization levels of a host IC chip. The chiplet may include a device layer and one or more metallization layers interconnecting passive and/or active devices into chiplet circuitry. The host IC may include a device layer and one or more metallization layers interconnecting passive and/or active devices into host chip circuitry. Features of one of the chiplet metallization layers may be directly bonded to features of one of the host IC metallization layers, interconnecting the two circuitries into a composite circuitry. A dielectric material may be applied over the chiplet. The dielectric and chiplet may be thinned with a planarization process, and additional metallization layers fabricated over the chiplet and host chip, for example to form first level interconnect interfaces. The composite IC chip structure may be assembled into a package substantially as a monolithic IC chip.

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