公开(公告)号：US08946823B2

公开(公告)日：2015-02-03

申请号：US14020510

申请日：2013-09-06

Applicant: Infineon Technologies AG

Inventor： Wolfgang Klein ,  Hans Taddiken ,  Winfried Bakalski

IPC: H01L23/62 ,  H01L23/60 ,  H01L27/02 ,  H01L29/861

CPC classification number: H01L23/60 ,  H01L27/0259 ,  H01L29/861 ,  H01L29/8618 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electrostatic discharge (ESD) protection element includes a collector area, a first barrier area, a semiconductor area, a second barrier area and an emitter area. The collector area has a first conductivity type. The first barrier area borders on the collector area and has a second conductivity type. The semiconductor area borders on the first barrier area and is an intrinsic semiconductor area, or has the first or second conductivity type and a dopant concentration which is lower than a dopant concentration of the first barrier area. The second barrier area borders on the semiconductor area and has the second conductivity type and a higher dopant concentration than the semiconductor area. The emitter area borders on the second barrier area and has the first conductivity type.

Abstract translation: 静电放电（ESD）保护元件包括集电区域，第一阻挡区域，半导体区域，第二阻挡区域和发射极区域。 集电区具有第一导电类型。 第一屏障区域与集电区域相邻，具有第二导电类型。 半导体区域与第一屏障区域相邻并且是本征半导体区域，或者具有低于第一阻挡区域的掺杂剂浓度的第一或第二导电类型和掺杂剂浓度。 第二阻挡区域与半导体区域相邻并且具有比半导体区域更高的第二导电类型和更高的掺杂剂浓度。 发射极区域与第二阻挡区域相邻并且具有第一导电类型。

公开(公告)号：US20140340181A1

公开(公告)日：2014-11-20

申请号：US13894096

申请日：2013-05-14

Applicant: Infineon Technologies AG

Inventor： Winfried Bakalski

IPC: H03J5/24

CPC classification number: H03J5/244 ,  H03J2200/10

Abstract: In accordance with an embodiment, a switchable capacitance circuit includes a plurality of capacitance-switch cells that each has a first semiconductor switching circuit and a capacitance circuit having a first terminal coupled to the first semiconductor switching circuit. A resistance of the first semiconductor switching circuit of a first switch-capacitance cell of the plurality of capacitance-switch cells is within a first tolerance of a resistance of the first semiconductor switching circuit of a second capacitance-switch cell of the plurality of capacitance-switch cells, and a capacitance of the capacitance circuit of the first capacitance-switch cell is within a second tolerance of a capacitance of the capacitance circuit of the second capacitance-switch cell.

Abstract translation: 根据实施例，可切换电容电路包括多个电容开关单元，每个电容开关单元具有第一半导体开关电路和具有耦合到第一半导体开关电路的第一端子的电容电路。 多个电容开关单元中的第一开关电容单元的第一半导体开关电路的电阻在多个电容开关单元中的第二电容开关单元的第一半导体开关电路的电阻的第一公差内， 开关单元，并且第一电容开关单元的电容电路的电容在第二电容开关单元的电容电路的电容的第二容限内。

公开(公告)号：US20140252540A1

公开(公告)日：2014-09-11

申请号：US13790117

申请日：2013-03-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Winfried Bakalski ,  Anton Steltenpohl

IPC: H01L23/28 ,  H01L23/50 ,  H01L21/78 ,  H01L23/538

CPC classification number: H01L23/28 ,  H01L21/561 ,  H01L21/78 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3121 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/50 ,  H01L23/538 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2224/81 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor substrate having a first main surface in which a recess is formed. Further, the semiconductor device includes an electrical interconnect structure which is arranged at a bottom of the recess. A semiconductor chip is located in the recess. The semiconductor chip includes a plurality of chip electrodes facing the electrical interconnect structure. Further, a plurality of electrically conducting elements is arranged in the electrical interconnect structure and electrically connected to the plurality of chip electrodes.

Abstract translation: 半导体器件包括具有形成凹部的第一主表面的半导体衬底。 此外，半导体器件包括设置在凹部的底部的电互连结构。 半导体芯片位于凹槽中。 半导体芯片包括面向电互连结构的多个芯片电极。 此外，多个导电元件布置在电互连结构中并电连接到多个芯片电极。

公开(公告)号：US20140104132A1

公开(公告)日：2014-04-17

申请号：US13651174

申请日：2012-10-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Winfried Bakalski ,  Anthony Thomas

IPC: H03H7/38 ,  H01Q1/50

CPC classification number: H03H7/38 ,  H01L23/66 ,  H01L27/0641 ,  H01L27/08 ,  H01L27/0808 ,  H01L27/1203 ,  H01L29/41733 ,  H01L29/42384 ,  H01L2223/6655 ,  H01L2223/6677 ,  H01L2924/0002 ,  H04B1/0458 ,  H04B1/18 ,  H01L2924/00

Abstract: An impedance matching network comprises a first and a second signal terminal and a reference potential terminal. The network further comprises a first shunt branch between the first signal terminal and the reference potential terminal, the first shunt branch comprising a variable inductive element and a first capacitive element. The impedance matching network also comprises a second shunt branch between the second signal terminal and the reference potential terminal and comprising a second capacitive element. A series branch between the first signal terminal and the second signal terminal comprises a third capacitive element. Optionally, the first, second, and/or third capacitive element may be implemented as a variable capacitive element. The variable capacitive element comprises a plurality of transistors, wherein a combination of off-capacitances Coff of the transistors provide an overall capacitance of the variable capacitive element as a function of at least two independent transistor control signals.

Abstract translation: 阻抗匹配网络包括第一和第二信号端子和参考电位端子。 网络还包括在第一信号端和参考电位端之间的第一分路支路，第一分路支路包括可变电感元件和第一电容元件。 阻抗匹配网络还包括在第二信号端子和参考电位端子之间的第二分路支路，并且包括第二电容元件。 第一信号端子和第二信号端子之间的串联分支包括第三电容元件。 可选地，第一，第二和/或第三电容元件可以被实现为可变电容元件。 可变电容元件包括多个晶体管，其中晶体管的关断电容Coff的组合提供作为至少两个独立晶体管控制信号的函数的可变电容元件的总体电容。

公开(公告)号：US20140001491A1

公开(公告)日：2014-01-02

申请号：US14020510

申请日：2013-09-06

Applicant: Infineon Technologies AG

Inventor： Wolfgang Klein ,  Hans Taddiken ,  Winfried Bakalski

IPC: H01L23/60

CPC classification number: H01L23/60 ,  H01L27/0259 ,  H01L29/861 ,  H01L29/8618 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electrostatic discharge (ESD) protection element includes a collector area, a first barrier area, a semiconductor area, a second barrier area and an emitter area. The collector area has a first conductivity type. The first barrier area borders on the collector area and has a second conductivity type. The semiconductor area borders on the first barrier area and is an intrinsic semiconductor area, or has the first or second conductivity type and a dopant concentration which is lower than a dopant concentration of the first barrier area. The second barrier area borders on the semiconductor area and has the second conductivity type and a higher dopant concentration than the semiconductor area. The emitter area borders on the second barrier area and has the first conductivity type.

Abstract translation: 静电放电（ESD）保护元件包括集电区域，第一阻挡区域，半导体区域，第二阻挡区域和发射极区域。 集电区具有第一导电类型。 第一屏障区域与集电区域相邻，具有第二导电类型。 半导体区域与第一屏障区域相邻并且是本征半导体区域，或者具有低于第一阻挡区域的掺杂剂浓度的第一或第二导电类型和掺杂剂浓度。 第二阻挡区域与半导体区域相邻并且具有比半导体区域更高的第二导电类型和更高的掺杂剂浓度。 发射极区域与第二阻挡区域相邻并且具有第一导电类型。

公开(公告)号：US20130278323A1

公开(公告)日：2013-10-24

申请号：US13918319

申请日：2013-06-14

Applicant: Infineon Technologies AG

Inventor： Winfried Bakalski ,  Hans Taddiken ,  Nikolay Ilkov ,  Herbert Kebinger

IPC: H03K17/16

CPC classification number: H02M3/07 ,  H03K17/161 ,  H03K17/6871 ,  H03K2217/0018

Abstract: A high-frequency switching circuit includes a high-frequency switching transistor, wherein a high-frequency signal-path extends via a channel-path of the high-frequency switching transistor. The high-frequency switching circuit includes a control circuit and the control circuit is configured to apply at least two different bias potentials to a substrate of the high-frequency switching transistor, depending on a control signal received by the control circuit.

Abstract translation: 高频开关电路包括高频开关晶体管，其中高频信号路径经由高频开关晶体管的沟道路径延伸。 高频开关电路包括控制电路，并且控制电路被配置为根据由控制电路接收的控制信号将至少两个不同的偏置电位施加到高频开关晶体管的衬底。