公开(公告)号：US10763420B2

公开(公告)日：2020-09-01

申请号：US16301498

申请日：2016-06-13

Applicant: Intel Corporation

Inventor： Zachary R. Yoscovits ,  David J. Michalak ,  Jeanette M. Roberts ,  Ravi Pillarisetty ,  James S. Clarke

IPC: H01L39/24 ,  H01L27/18 ,  H01L39/02 ,  H01L39/22 ,  H01L39/12 ,  H01L39/08

Abstract: Described herein are structures that include Josephson Junctions (JJs) to be used in superconducting qubits of quantum circuits disposed on a substrate. The JJs of these structures are fabricated using an approach that can be efficiently used in large scale manufacturing, providing a substantial improvement with respect to conventional approaches which include fabrications steps which are not manufacturable. In one aspect of the present disclosure, the proposed approach includes providing a patterned superconductor layer over a substrate, providing a layer of surrounding dielectric over the patterned superconductor layer, and providing a via opening in the layer of surrounding dielectric over a first portion of the patterned superconductor layer. The proposed approach further includes depositing in the via opening a first superconductor, a barrier dielectric, and a second superconductor to form, respectively, a base electrode, a tunnel barrier layer, and a top electrode of the JJ.

公开(公告)号：US10756202B2

公开(公告)日：2020-08-25

申请号：US16307724

申请日：2016-06-08

Applicant: Intel Corporation

Inventor： Jeanette M. Roberts ,  Ravi Pillarisetty ,  David J. Michalak ,  Zachary R. Yoscovits ,  James S. Clarke ,  Adel A. Elsherbini

IPC: H01L29/66 ,  H01L29/12 ,  H01L29/423 ,  H01L29/76 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/06 ,  H01L29/165 ,  H01L29/778

Abstract: Disclosed herein are quantum dot device packages, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device package may include a die having a quantum dot device, wherein the quantum dot device includes a quantum well stack, gates disposed above the quantum well stack, and conductive pathways coupled between associated ones of the gates and conductive contacts of the die. The quantum dot device package may also include a package substrate, wherein conductive contacts are disposed on the package substrate, and first level interconnects are disposed between the die and the package substrate, coupling the conductive contacts of the die with associated conductive contacts of the package substrate.

公开(公告)号：US10748961B2

公开(公告)日：2020-08-18

申请号：US16307979

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： David J. Michalak ,  Ravi Pillarisetty ,  Zachary R. Yoscovits ,  Jeanette M. Roberts ,  James S. Clarke

IPC: H01L27/18 ,  G06N10/00 ,  H01L23/522 ,  H01L23/66 ,  H01L39/02 ,  H01L39/22 ,  H01L39/24

Abstract: Described herein are structures that include interconnects for providing electrical connectivity in superconducting quantum circuits. One structure includes a first and a second interconnects provided over a surface of an interconnect support layer, e.g. a substrate, on which superconducting qubits are provided, a lower interconnect provided below such surface (i.e. below-plane interconnect), and vias for providing electrical interconnection between the lower interconnect and each of the first and second interconnects. Providing below-plane interconnects in superconducting quantum circuits allows realizing superconducting and mechanically stable interconnects. Implementing below-plane interconnects by bonding of two substrates, material for which could be selected, allows minimizing the amount of spurious two-level systems in the areas surrounding below-plane interconnects while allowing different choices of materials to be used. Methods for fabricating such structures are disclosed as well.

公开(公告)号：US10748960B2

公开(公告)日：2020-08-18

申请号：US16307976

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： David J. Michalak ,  Jeanette M. Roberts ,  Ravi Pillarisetty ,  Zachary R. Yoscovits ,  James S. Clarke

IPC: H01L27/18 ,  H01L23/522 ,  H01L39/02 ,  H01L39/22 ,  H01L39/24 ,  H01L21/74 ,  G06N10/00

Abstract: Described herein are structures that include interconnects for providing electrical connectivity in superconducting quantum circuits. In one aspect of the present disclosure, a structure includes a first and a second interconnects provided over a surface of an interconnect support layer on which superconducting qubits are provided (which could be a substrate), a lower interconnect provided below such surface, and vias for providing electrical interconnection between the lower interconnect and each of the first and second interconnects. The lower interconnect includes a material of the interconnect support layer doped to be superconductive. Providing below-plane interconnects in superconducting quantum circuits allows realizing superconducting and mechanically stable interconnects. Implementing below-plane interconnects by doping the interconnect support layer, material for which could be selected, allows minimizing the amount of spurious TLS's in the areas surrounding below-plane interconnects. Methods for fabricating such structures are disclosed as well.

公开(公告)号：US10565515B2

公开(公告)日：2020-02-18

申请号：US16013384

申请日：2018-06-20

Applicant: Intel Corporation

Inventor： Lester Lampert ,  Ravi Pillarisetty ,  Nicole K. Thomas ,  Hubert C. George ,  Jeanette M. Roberts ,  David J. Michalak ,  Roman Caudillo ,  Zachary R. Yoscovits ,  James S. Clarke

IPC: G06N10/00 ,  B82Y10/00 ,  H01L39/22 ,  H03K19/195 ,  H01L27/18 ,  H01R24/56

Abstract: Embodiments of the present disclosure describe quantum circuit assemblies utilizing triaxial cables to communicate signals to/from quantum circuit components. One assembly includes a cooling apparatus for cooling a quantum circuit component that includes at least one qubit device. The cooling apparatus includes at least one triaxial connector for providing signals to and/or receiving signals from the quantum circuit component using one or more triaxial cables. Other assemblies include quantum circuit components and various electronic components (e.g. attenuators, filters, or amplifiers) for use within the cooling apparatus, adapted to be used with triaxial cables by incorporating triaxial connectors as well.

公开(公告)号：US20190363181A1

公开(公告)日：2019-11-28

申请号：US16097730

申请日：2016-06-29

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Van H. Le ,  Jeanette M. Roberts ,  James S. Clarke ,  Zachary R. Yoscovits ,  David J. Michalak

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/12 ,  H01L29/786

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer, a doped layer, and a barrier layer disposed between the doped layer and the quantum well layer; and gates disposed above the quantum well stack. The doped layer may include a first material and a dopant, the first material may have a first diffusivity of the dopant, the barrier layer may include a second material having a second diffusivity of the dopant, and the second diffusivity may be less than the first diffusivity.

公开(公告)号：US10475912B2

公开(公告)日：2019-11-12

申请号：US15900655

申请日：2018-02-20

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  Ravi Pillarisetty ,  Kanwaljit Singh ,  Hubert C. George ,  Jeanette M. Roberts ,  David J. Michalak ,  Roman Caudillo ,  Zachary R. Yoscovits ,  Lester Lampert ,  James S. Clarke ,  Willy Rachmady

IPC: H01L39/00 ,  H01L29/778 ,  H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  G06N10/00 ,  H01L39/02 ,  H01L29/82

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a layer of gate dielectric above the quantum well stack; a first gate metal and a second gate metal above the layer of gate dielectric; and a gate wall between the first gate metal and the second gate metal, wherein the gate wall is above the layer of gate dielectric, and the gate wall includes a first dielectric material and a second dielectric material different from the first dielectric material.

公开(公告)号：US20190305037A1

公开(公告)日：2019-10-03

申请号：US16307976

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： David J. Michalak ,  Jeanette M. Roberts ,  Ravi Pillarisetty ,  Zachary R. Yoscovits ,  James S. Clarke

IPC: H01L27/18 ,  H01L39/22 ,  H01L23/522 ,  H01L39/02 ,  H01L39/24

Abstract: Described herein are structures that include interconnects for providing electrical connectivity in superconducting quantum circuits. In one aspect of the present disclosure, a structure includes a first and a second interconnects provided over a surface of an interconnect support layer on which superconducting qubits are provided (which could be a substrate), a lower interconnect provided below such surface, and vias for providing electrical interconnection between the lower interconnect and each of the first and second interconnects. The lower interconnect includes a material of the interconnect support layer doped to be superconductive. Providing below-plane interconnects in superconducting quantum circuits allows realizing superconducting and mechanically stable interconnects. Implementing below-plane interconnects by doping the interconnect support layer, material for which could be selected, allows minimizing the amount of spurious TLS's in the areas surrounding below-plane interconnects. Methods for fabricating such structures are disclosed as well.

公开(公告)号：US20190288176A1

公开(公告)日：2019-09-19

申请号：US16302049

申请日：2016-06-13

Applicant: Intel Corporation

Inventor： Zachary R. Yoscovits ,  David J. Michalak ,  Jeanette M. Roberts ,  Ravi Pillarisetty ,  James S. Clarke

IPC: H01L39/22 ,  H01L39/24 ,  G06N10/00

Abstract: Described herein are structures that include Josephson Junctions to be used in superconducting qubits of quantum circuits disposed on a substrate. In one aspect of the present disclosure, at least a part of a Josephson Junction of a superconducting qubit is suspended over a substrate, forming a gap between at least the portion of the Josephson Junction and the substrate. Moving at least a portion of the Josephson Junction further away from the substrate by suspending at least a part of the Junction over the substrate allows reducing spurious two-level systems present in the vicinity of the Junction, which, in turn, improves on the qubit decoherence problem. Methods for fabricating such structures are disclosed as well.

公开(公告)号：US20190259850A1

公开(公告)日：2019-08-22

申请号：US16307853

申请日：2016-06-09

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Van H. Le ,  Jeanette M. Roberts ,  David J. Michalak ,  James S. Clarke ,  Zachary R. Yoscovits

IPC: H01L29/423 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

Abstract: Disclosed herein are quantum dot devices with trenched substrates, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate having a trench disposed therein, wherein a bottom of the trench is provided by a first material, and a quantum well stack at least partially disposed in the trench. A material of the quantum well stack may be in contact with the bottom of the trench, and the material of the quantum well stack may be different from the first material.