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公开(公告)号：US20090267084A1
公开(公告)日：2009-10-29
申请号：US12109558
申请日：2008-04-25
申请人： Christoph Bilger , Peter Gregorius , Michael Bruennert , Maurizio Skerlj , Wolfgang Walthes , Johannes Stecker , Hermann Ruckerbauer , Dirk Scheideler , Roland Barth
发明人： Christoph Bilger , Peter Gregorius , Michael Bruennert , Maurizio Skerlj , Wolfgang Walthes , Johannes Stecker , Hermann Ruckerbauer , Dirk Scheideler , Roland Barth
CPC分类号： H01L23/48 , H01L25/0657 , H01L25/167 , H01L2224/05571 , H01L2224/05573 , H01L2224/16 , H01L2224/32145 , H01L2225/06527 , H01L2924/00014 , H01L2924/01019 , H01L2224/05599
摘要： An integrated circuit includes a device stack including: a memory device with a first wireless coupling element, and a semiconductor device with a second wireless coupling element. The first and second wireless coupling elements are arranged face-to-face and are configured to provide a wireless connection between the memory device and the semiconductor device.
摘要翻译： 集成电路包括：器件堆叠，其包括：具有第一无线耦合元件的存储器件，以及具有第二无线耦合元件的半导体器件。 第一和第二无线耦合元件面对面布置并且被配置为在存储器件和半导体器件之间提供无线连接。
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82.发明授权Method and device for estimating channel properties of a transmission channel 有权用于估计传输信道的信道特性的方法和装置公开(公告)号：US07561639B2
公开(公告)日：2009-07-14
申请号：US10970516
申请日：2004-10-21
申请人： Peter Gregorius , Paul Georg Lindt , Heinz Mattes
发明人： Peter Gregorius , Paul Georg Lindt , Heinz Mattes
IPC分类号： H04L27/06
CPC分类号： H04L47/10
摘要： To estimate physical properties of a wired or wireless transmission channel it is proposed to sample a signal, received via the transmission channel, for example a system response of the corresponding transmission system, in order, on the basis of the sampled values thus obtained, to ascertain the moments of the order 0 . . . n of the received signal. Using these moments of the order 0 . . . n, n parameters of a transmission function of the transmission channel can be determined, wherein the parameters can be polynomial coefficients, zero points or coefficients of a residual notation of the transmission function. Using this transmission function the physical properties of the transmission channel, such as the attenuation and dispersion properties, can be determined exactly or at least approximately assessed.
摘要翻译： 为了估计有线或无线传输信道的物理特性，提出了通过传输信道接收的信号，例如相应传输系统的系统响应，以这样获得的采样值为基础 确定订单的时刻0。 。 。 n的接收信号。 使用订单0的这些时刻。 。 。 可以确定传输信道的传输函数的n，n个参数，其中参数可以是传输函数的多项式系数，零点或残差符号的系数。 使用这种传输功能，传输通道的物理特性，如衰减和色散特性，可以精确地或至少近似评估来确定。
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公开(公告)号：US07523250B2
公开(公告)日：2009-04-21
申请号：US11509092
申请日：2006-08-24
申请人： Paul Wallner , Andre Schäfer , Peter Gregorius
发明人： Paul Wallner , Andre Schäfer , Peter Gregorius
CPC分类号： G11C8/12 , G11C7/1051 , G11C2207/107
摘要： A semiconductor memory system includes a semiconductor memory chip in which data, command, and address signals are transmitted serially between a memory controller and the semiconductor memory chip in signal frames in correspondence with a predetermined protocol. In a receive signal path within the semiconductor memory chip, a frame decoder for decoding the signal frames is arranged following a receiving interface device, and between the frame decoder and a memory core, an intermediate storage device is arranged which has a cell array including a multiplicity of memory cells, and an addressing and selector circuit to which address signals decoded by the frame decoder from command and/or write signal frames supplied by the memory controller are applied, for addressing the cell array and for selecting the write data to be written into the cell array and to be read out of the cell array.
摘要翻译： 半导体存储器系统包括半导体存储器芯片，其中数据，命令和地址信号在与预定协议相对应的信号帧中的存储器控制器和半导体存储器芯片之间串行发送。 在半导体存储器芯片内的接收信号路径中，用于对信号帧进行解码的帧解码器被布置在接收接口设备之后，并且在帧解码器和存储器核心之间，布置中间存储设备，其具有包括单元阵列 多个存储器单元，以及寻址和选择器电路，由帧解码器从由存储器控制器提供的命令和/或写入信号帧解码的地址信号被应用于寻址单元阵列并用于选择要写入的写入数据 进入单元阵列并从单元阵列中读出。
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公开(公告)号：US07515075B1
公开(公告)日：2009-04-07
申请号：US11856353
申请日：2007-09-17
IPC分类号： H03M9/00
摘要： A circuit includes a data conversion circuit including a first input configured to receive a first serial data stream, a second input configured to receive a second serial data stream, and a third input configured to receive a third serial data stream. A first sampling circuit is coupled to the first, second, and third inputs and is configured to sample the first to third data streams based on a plurality of clock signals and to generate a corresponding plurality of first sampled signals. A second sampling circuit is configured to sample the plurality of first sampled signals based on a further clock signal. The further clock signal has a clock frequency different from a clock frequency underlying the first to third serial data streams.
摘要翻译： 电路包括数据转换电路，其包括被配置为接收第一串行数据流的第一输入，被配置为接收第二串行数据流的第二输入和被配置为接收第三串行数据流的第三输入。 第一采样电路耦合到第一，第二和第三输入，并且被配置为基于多个时钟信号对第一至第三数据流进行采样，并且生成对应的多个第一采样信号。 第二采样电路被配置为基于另一个时钟信号对多个第一采样信号进行采样。 另外的时钟信号的时钟频率不同于第一到第三串行数据流的时钟频率。
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公开(公告)号：US20090073010A1
公开(公告)日：2009-03-19
申请号：US11856353
申请日：2007-09-17
IPC分类号： H03M9/00
摘要： A circuit includes a data conversion circuit including a first input configured to receive a first serial data stream, a second input configured to receive a second serial data stream, and a third input configured to receive a third serial data stream. A first sampling circuit is coupled to the first, second, and third inputs and is configured to sample the first to third data streams based on a plurality of clock signals and to generate a corresponding plurality of first sampled signals. A second sampling circuit is configured to sample the plurality of first sampled signals based on a further clock signal. The further clock signal has a clock frequency different from a clock frequency underlying the first to third serial data streams.
摘要翻译： 电路包括数据转换电路，其包括被配置为接收第一串行数据流的第一输入，被配置为接收第二串行数据流的第二输入和被配置为接收第三串行数据流的第三输入。 第一采样电路耦合到第一，第二和第三输入，并且被配置为基于多个时钟信号对第一至第三数据流进行采样，并且生成对应的多个第一采样信号。 第二采样电路被配置为基于另一个时钟信号对多个第一采样信号进行采样。 另外的时钟信号的时钟频率不同于第一到第三串行数据流的时钟频率。
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公开(公告)号：US07414917B2
公开(公告)日：2008-08-19
申请号：US11192335
申请日：2005-07-29
IPC分类号： G11C8/00
摘要： Semiconductor memory modules and semiconductor memory systems using the same are described herein. The modules divide a conventional DIMM into a series of separate, smaller memory modules. Each memory module includes at least one semiconductor memory chip arranged on a substrate; CAwD signal input lines arranged on the substrate in a first predetermined line number and connecting one of the semiconductor memory chips to CAwD input signal pins on the substrate; and rD signal output lines arranged on the substrate in a second predetermined line number and connecting the one or a last semiconductor memory to a second number of rD output signal pins of the substrate. In a semiconductor memory system including the semiconductor memory modules, each memory module is separately connected to a memory controller by the CAwD signal input lines and the rD signal output lines in a respective point-to-point fashion.
摘要翻译： 本文描述了使用其的半导体存储器模块和半导体存储器系统。 这些模块将常规DIMM分成一系列独立的较小内存模块。 每个存储器模块包括布置在衬底上的至少一个半导体存储器芯片; CAwD信号输入线，以第一预定行号排列在基板上，并将半导体存储器芯片之一连接到基板上的CAwD输入信号引脚; 和rD信号输出线，以第二预定行号排列在基板上，并将一个或最后一个半导体存储器连接到基板的第二数量的rD输出信号引脚。 在包括半导体存储器模块的半导体存储器系统中，每个存储器模块通过CAwD信号输入线和rD信号输出线分别以点对点的方式连接到存储器控制器。
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公开(公告)号：US07391657B2
公开(公告)日：2008-06-24
申请号：US11751984
申请日：2007-05-22
申请人： Paul Wallner , Martin Streibl , Manfred Menke , Yukio Fukuzo , Christian Sichert , Peter Gregorius
发明人： Paul Wallner , Martin Streibl , Manfred Menke , Yukio Fukuzo , Christian Sichert , Peter Gregorius
CPC分类号： G11C7/1006 , G11C11/4096
摘要： A semiconductor memory chip includes: a reception interface section for receiving external data, command, and address signals in form of serial signal frames; an intermediate data buffer for intermediately storing write data and, optionally, write data mask bits to be written to a memory cell array; a memory core having a bank organized memory cell array; a decoder section for decoding an address derived from a signal frame received from the reception interface section for writing/reading data in/from one or more memory banks of the memory cell array in accordance with a write/read command within one or more received signal frames; and a frame decoder provided as an interface between the reception interface section and the memory core for decoding one or more commands included in one or more frames and outputting data addresses, command, and read/write access indication signals to the memory core and to the intermediate data buffer.
摘要翻译： 半导体存储器芯片包括：接收接口部分，用于以串行信号帧的形式接收外部数据，命令和地址信号; 中间数据缓冲器，用于中间存储写入数据，以及可选地写入要写入存储单元阵列的数据屏蔽位; 具有存储体组织的存储单元阵列的存储器核心; 解码器部分，用于对从接收接口部分接收的信号帧导出的地址进行解码，用于根据在一个或多个接收信号中的写入/读取命令向/从存储器单元阵列的一个或多个存储器组写入/读取数据 框架 以及帧解码器，被设置为在接收接口部分和存储器核心之间的接口，用于解码包括在一个或多个帧中的一个或多个命令，并将数据地址，命令和读/写访问指示信号输出到存储器核心 中间数据缓冲区。
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公开(公告)号：US07378892B2
公开(公告)日：2008-05-27
申请号：US11194509
申请日：2005-08-01
申请人： Peter Gregorius
发明人： Peter Gregorius
CPC分类号： H03L7/0814 , H03K5/133 , H03K5/135 , H03K5/1565 , H03K2005/00019 , H03L7/0805
摘要： A device for setting a clock delay is proposed, wherein delayed output clock signals are generated with the aid of delaying means by delaying an input clock signal. The delaying means are configured to provide several differently delayed clock signals simultaneously. The device is configured to generate the at least one output clock signal depending on the differently delayed clock signals with a settable phase relationship to the non-delayed input clock signal, wherein the phase relationship is settable independently of the delay provided by the delaying means. It is particularly provided that the phase relationship between the delayed output clock signal and the non-delayed input clock signal is automatically controlled to a desired phase relationship independently of the delay supplied by the delaying means.
摘要翻译： 提出了一种用于设置时钟延迟的装置，其中通过延迟输入时钟信号借助于延迟装置产生延迟的输出时钟信号。 延迟装置被配置为同时提供若干不同延迟的时钟信号。 该装置被配置为根据具有与非延迟输入时钟信号的可设置的相位关系的不同延迟的时钟信号来产生至少一个输出时钟信号，其中相位关系可独立于由延迟装置提供的延迟来设置。 特别地，延迟输出时钟信号和非延迟输入时钟信号之间的相位关系被自动地控制到期望的相位关系，而与延迟装置提供的延迟无关。
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公开(公告)号：US07313211B2
公开(公告)日：2007-12-25
申请号：US10407033
申请日：2003-04-03
申请人： Peter Gregorius , Edoardo Prete , Paul Wallner
发明人： Peter Gregorius , Edoardo Prete , Paul Wallner
IPC分类号： H03D3/24
CPC分类号： H03L7/091 , H04L7/0083 , H04L7/033
摘要： The present invention relates to a method and apparatus for generating an output signal in dependence on a phase difference between two periodic signals. The present invention is particularly useful in phase locked loops and delay locked loops, in which a controllable oscillator or a controllable delay device is controlled on the basis of the phase difference determined by means of phase detection, in such a way that a control signal can be obtained, the phase lag or frequency of which has a firm relationship to the reference signal.
摘要翻译： 本发明涉及根据两个周期信号之间的相位差产生输出信号的方法和装置。 本发明在锁相环和延迟锁定环特别有用，其中基于通过相位检测确定的相位差来控制可控振荡器或可控延迟器件，使得控制信号可以 获得，相位滞后或其频率与参考信号具有牢固的关系。
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公开(公告)号：US20070280007A1
公开(公告)日：2007-12-06
申请号：US11735971
申请日：2007-04-16
申请人： Paul Wallner , Peter Gregorius
发明人： Paul Wallner , Peter Gregorius
IPC分类号： G11C7/10
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/106 , G11C7/20 , G11C11/4072 , G11C11/4076 , G11C11/4093 , G11C11/4096
摘要： A memory device comprising a memory cell array; an input circuit providing drive signals to the memory cell array dependent on externally received command data; an output buffer buffering data read out from the memory cell array; and a timer driving the output buffer such that the buffered data are provided at an output after an adjustable time interval has elapsed, the adjustable time interval beginning with the provision of the drive signals.
摘要翻译： 一种存储器件，包括存储单元阵列; 输入电路，其根据外部接收到的命令数据向存储单元阵列提供驱动信号; 缓冲从存储单元阵列读出的数据的输出缓冲器; 以及驱动输出缓冲器的定时器，使得缓冲的数据在经过可调整时间间隔之后的输出处提供，可调整的时间间隔从提供驱动信号开始。
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