公开(公告)号：US06661060B2

公开(公告)日：2003-12-09

申请号：US10213613

申请日：2002-08-07

Applicant: Jian-Hsing Lee ,  Kuo-Reay Peng ,  Shih-Chyi Wong

Inventor： Jian-Hsing Lee ,  Kuo-Reay Peng ,  Shih-Chyi Wong

IPC: H01L2362

CPC classification number: H01L27/0251 ,  H01L27/0727

Abstract: An ESD protection device for the protection of MOS circuits from high ESD voltages by arranging an N-well of very short length in a P-well or P-substrate. Diffused into this N-well is a P+ diffusion. Together they form a diode and part of a parasitic pnp bipolar transistor which is shared by two parasitic SCRs. The junction capacitance of this N-well is very low and in the order of 0.03 pF. Disposed to either side of this N-well is an NMOS transistor which has its drain (an N+ diffusion) next to the it. The drain and the P+ diffusion are coupled together and connect to a chip pad, which receives the ESD. The chip pad couples to the MOS circuits to be protected. The junction capacitance of both drains combined is in the order of 0.24 pF, so that the junction capacitance of the N-well is about one tenth of that of both drains. A P+ diffusion) is located on either side of each source (N+ diffusion) and together are coupled to a reference potential. An ESD pulse applied to the chip pad exceeds the electric field strength of the channel of the NMOS transistors and drives them into conduction and snapback mode. Hole and electron currents between components of the NMOS transistors and the N-well and its P+ diffusion next turn on both SCRs and conduct the ESD current safely from the chip pad to the source and ground.

公开(公告)号：US06576934B2

公开(公告)日：2003-06-10

申请号：US10278135

申请日：2002-10-22

Applicant: Tao Cheng ,  Jian-Hsing Lee

Inventor： Tao Cheng ,  Jian-Hsing Lee

IPC: H01L2974

CPC classification number: H01L27/0262

Abstract: An embedded SCR in conjunction with a Gated-NMOS is created for protecting a chip input or output pad from ESD, by inserting a p+ diffusion and the n-well in the drain side and a part of the drain to forms a low-trigger, high efficiency SCR. The device layout is such that the drain connection is tightly tied together at the p+ diffusion and the n+ drain making that connection very short and, thereby, preventing latch-up. The parasitic SCR is contained entirely within the n+ diffusion (the source of the grounded gate NMOS transistor) at either side of the structure and, therefore, called an embedded SCR. For a 12 volt I/O device each of two n+ drains is placed in its own n-type doped drain (ndd) area straddling halfway the n-well. The structure is repeated as required and a p+ diffusion is implanted at both perimeters and connected to the nearest n+ source and a reference voltage.

Abstract translation: 通过在漏极侧和漏极的一部分插入p +扩散和n阱，形成嵌入式SCR，与栅极NMOS相结合，用于保护芯片输入或输出焊盘免受ESD影响，形成低触发， 高效SCR。 器件布局使得漏极连接在p +扩散和n +漏极紧密连接在一起，使得该连接非常短，从而防止闩锁。 寄生SCR完全包含在结构两侧的n +扩散（接地栅极NMOS晶体管的源极）内，因此被称为嵌入式SCR。 对于12伏I / O设备，两个n +漏极中的每一个都放置在跨越n-阱一半的其自身的n型掺杂漏极（ndd）区域中。 根据需要重复该结构，并且在两个周边注入p +扩散并连接到最近的n +源和参考电压。

公开(公告)号：US06448123B1

公开(公告)日：2002-09-10

申请号：US09785107

申请日：2001-02-20

Applicant: Jian-Hsing Lee ,  Kuo-Reay Peng ,  Shih-Chyi Wong

Inventor： Jian-Hsing Lee ,  Kuo-Reay Peng ,  Shih-Chyi Wong

IPC: H01L218238

CPC classification number: H01L27/0251 ,  H01L27/0727

Abstract: An ESD protection device for the protection of MOS circuits from high ESD voltages by arranging an N-well of very short length in a P-well or P-substrate. Diffused into this N-well is a P+ diffusion. Together they form a diode and part of a parasitic pnp bipolar transistor which is shared by two parasitic SCRs. The junction capacitance of this N-well is very low and in the order of 0.03 pF. Disposed to either side of this N-well is an NMOS transistor which has its drain (an N+ diffusion) next to the it. The drain and the P+ diffusion are coupled together and connect to a chip pad, which receives the ESD. The chip pad couples to the MOS circuits to be protected. The junction capacitance of both drains combined is in the order of 0.24 pF, so that the junction capacitance of the N-well is about one tenth of that of both drains. A P+ diffusion is located on either side of each source (N+ diffusion) and together are coupled to a reference potential. An ESD pulse applied to the chip pad exceeds the electric field strength of the channel of the NMOS transistors and drives them into conduction and snapback mode. Hole and electron currents between components of the NMOS transistors and the N-well and its P+ diffusion next turn on both SCRs and conduct the ESD current safely from the chip pad to the source and ground.

Abstract translation: 一种ESD保护器件，用于通过在P阱或P-衬底中布置非常短的长度的N阱来保护MOS电路免受高ESD电压的影响。 扩散到这个N阱是一个P +扩散。 它们一起形成二极管和由两个寄生SCR共享的寄生pnp双极晶体管的一部分。 该N阱的结电容非常低，为0.03pF。 配置在该N阱的任一侧的是NMOS晶体管，其旁边有漏极（N +扩散）。 漏极和P +扩散耦合在一起并连接到接收ESD的芯片焊盘。 芯片焊盘耦合到要保护的MOS电路。 组合的两个排水管的结电容量为0.24pF，使得N阱的结电容大约是两个排水管的结电容的十分之一。 P +扩散位于每个源（N +扩散）的两侧，并且一起耦合到参考电位。 施加到芯片焊盘的ESD脉冲超过NMOS晶体管的沟道的电场强度，并将其驱动为导通和快速恢复模式。 NMOS晶体管和N阱的组件之间的空穴和电子电流及其P +扩散接下来导通两个SCR，并将ESD电流安全地从芯片焊盘传导到源极和接地。

公开(公告)号：US06441438B1

公开(公告)日：2002-08-27

申请号：US09709597

申请日：2000-11-13

Applicant: Jiaw-Ren Shih ,  Jian-Hsing Lee ,  Huey-Liang Hwang

Inventor： Jiaw-Ren Shih ,  Jian-Hsing Lee ,  Huey-Liang Hwang

IPC: H01L2362

CPC classification number: H01L27/027 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An ESD protection structure that when connected between an input/output pad on a semiconductor substrate and a reference voltage source, will protect internal circuits formed on the semiconductor substrate from over stress due to excessively high voltages of an ESD voltage source. The ESD protection structure has a uniform discharge current to prevent damage to the ESD protection device thus allowing increased protection to the internal circuits. The ESD protection device has at least one source region that is the emitters of parasitic transistors connected to the reference voltage source and at least one drain region that is the collectors of the parasitic transistors connected to the junction of the input/output pad and the internal circuitry. The ESD protection device further has at least one gate electrode formed above a channel region. The channel region is the region is between each of the source regions and the drain regions. The gate electrodes are connected to the reference voltage source. Each gate electrode has a variable length and thus the channel region has a variable length. The channel region is the base of the parasitic transistors formed by the ESD protection structure. The variable length of the channel region and thus the base of the parasitic transistors create an ESD current that is distributed uniformly over said ESD protection structure.

Abstract translation: 当连接在半导体衬底上的输入/输出焊盘与参考电压源之间时，ESD保护结构将保护由于ESD电压源的过高电压而在半导体衬底上形成的内部电路免受过度应力。 ESD保护结构具有均匀的放电电流，以防止ESD保护器件的损坏，从而允许增加对内部电路的保护。 ESD保护器件具有至少一个源极区域，其是连接到参考电压源的寄生晶体管的发射极，以及连接到输入/输出焊盘和内部的结的寄生晶体管的集电极的至少一个漏极区域 电路。 ESD保护器件还具有形成在通道区域上方的至少一个栅电极。 沟道区域是在源极区域和漏极区域中的每一个之间的区域。 栅电极连接到参考电压源。 每个栅电极具有可变长度，因此沟道区具有可变长度。 通道区域是由ESD保护结构形成的寄生晶体管的基极。 沟道区域的可变长度以及寄生晶体管的基极产生均匀分布在所述ESD保护结构上的ESD电流。

公开(公告)号：US06414532B1

公开(公告)日：2002-07-02

申请号：US09963596

申请日：2001-09-27

Applicant: Hung Der Su ,  Jian-Hsing Lee ,  Yi-Hsun Wu ,  Mau-Lin Wu

Inventor： Hung Der Su ,  Jian-Hsing Lee ,  Yi-Hsun Wu ,  Mau-Lin Wu

IPC: H03K508

CPC classification number: H01L27/0266

Abstract: An I/O ESD protection circuit is provided utilizing a driver circuit, an ESD protection circuit, a Vcc/Vss protection circuit, and a clamping circuit. The driver circuit and the ESD protection circuit each comprise a NMOS cascode circuit. NMOS transistors and biasing resistive means comprise the Vcc/Vss protection circuit. The clamping circuit is a diode coupled between the I/O pad of the protection circuit and the gate of that NMOS transistor. In an ESD event the diode turns on the NMOS transistor of the Vcc/Vss protection circuit , thus clamping off the first transistor of both NMOS cascode circuits. The clamping inhibits the gate of those first two transistors to be coupled up by an ESD voltage and creates a parasitic bipolar transistor in each cascode circuit. The parasitic bipolar transistors provide a uniform current flow in the buried area of the P-well of both NMOS cascode circuits.

Abstract translation: 使用驱动电路，ESD保护电路，Vcc / Vss保护电路和钳位电路来提供I / O ESD保护电路。 驱动电路和ESD保护电路各自包括NMOS共源共栅电路。 NMOS晶体管和偏置电阻装置包括Vcc / Vss保护电路。 钳位电路是耦合在保护电路的I / O焊盘和该NMOS晶体管的栅极之间的二极管。 在ESD事件中，二极管导通Vcc / Vss保护电路的NMOS晶体管，因此钳位了两个NMOS共源共栅电路的第一个晶体管。 钳位禁止这些前两个晶体管的栅极通过ESD电压耦合，并在每个共源共栅电路中产生寄生双极晶体管。 寄生双极晶体管在两个NMOS共源共栅电路的P阱的掩埋区域中提供均匀的电流。

公开(公告)号：US06306695B1

公开(公告)日：2001-10-23

申请号：US09407110

申请日：1999-09-27

Applicant: Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Shui-Hung Chen ,  Yi-Hsun Wu

Inventor： Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Shui-Hung Chen ,  Yi-Hsun Wu

IPC: H01L2100

CPC classification number: H01L27/0277 ,  H01L27/0259 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An ESD protection circuit that will prevent internal circuits of an integrated circuit is formed on a semiconductor substrate to prevent damage during extreme voltage levels from an ESD voltage source and is connected to an input/output pad. A plurality of drains of multiple MOS FET's is formed within the surface of the semiconductor substrate and are each connected to the input/output pad. A plurality of sources of the multiple MOS FET's is formed within the surface of the semiconductor substrate and are placed at a distance from the plurality of drains and are connected to a ground reference potential. Pairs of the plurality of sources are adjacent to each other. A plurality of isolation regions placed between each source of the pairs of sources and are allowed to float. The multiple MOS FET's have a plurality of parasitic bipolar junction transistors. When contacting an ESD voltage source to the collectors of the plurality of parasitic bipolar junction transistors, the junction formed between the collector and the base of the parasitic bipolar junction transistor enters into avalanche breakdown. The avalanche breakdown generates a large current through the substrate bulk resistances that is sufficiently large as to cause the base emitter junctions of all the parasitic bipolar junction transistors and turn on the parasitic bipolar junction transistors. The conduction of all the parasitic bipolar junction transistors is sufficient to cause the ESD voltage to be discharged thus preventing damage to the internal circuitry.

Abstract translation: 在半导体衬底上形成防止集成电路的内部电路的ESD保护电路，以防止在来自ESD电压源的极端电压电平期间的损坏并连接到输入/输出焊盘。 多个MOS FET的漏极形成在半导体衬底的表面内，并且各自连接到输入/输出焊盘。 多个MOS FET的多个源极形成在半导体衬底的表面内并且被放置在与多个漏极相距一定距离处并连接到接地参考电位。 多个源的对彼此相邻。 放置在源对之间的每个源之间并被允许浮动的多个隔离区域。 多个MOS FET具有多个寄生双极结型晶体管。 当将ESD电压源接触到多个寄生双极结型晶体管的集电极时，在集电极与寄生双极结型晶体管的基极之间形成的结形成为雪崩击穿。 雪崩击穿通过衬底体电阻产生大的电流，该电阻足够大，以致引起所有寄生双极结型晶体管的基极发射极结并导通寄生双极结型晶体管。 所有寄生双极结晶体管的导通足以使ESD电压放电，从而防止对内部电路的损坏。

公开(公告)号：US06268992B1

公开(公告)日：2001-07-31

申请号：US09292362

申请日：1999-04-15

Applicant: Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Yi-Hsun Wu ,  Jing-Meng Liu

Inventor： Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Yi-Hsun Wu ,  Jing-Meng Liu

IPC: H02H322

CPC classification number: H01L27/0262 ,  H01L29/87

Abstract: Circuits, device structures and methods are disclosed which protect CMOS semiconductor devices, having oxides as thin as 32 Angstrom, from electrostatic discharge (ESD) by utilizing a parasitic silicon controlled rectifier (SCR), intrinsic to the semiconductor device. The protection is afforded by providing low voltage triggering of the parasitic SCR in the order of 1.2 Volt. Triggering at such low voltages is made possible by means of a displacement current trigger which causes components of the SCR (parasitic npn and pnp bipolar transistors) to conduct, i.e., to trigger the SCR. The displacement current is realized by a junction capacitance, which is connected on one side to the pad to be protected and on the other side to terminals of the aforementioned parasitic bipolar transistors. Two ways of realizing the junction capacitance are disclosed.

公开(公告)号：US06258672B1

公开(公告)日：2001-07-10

申请号：US09252630

申请日：1999-02-18

Applicant: Jiaw-Ren Shih ,  Jian-Hsing Lee ,  Huey-Liang Hwang

Inventor： Jiaw-Ren Shih ,  Jian-Hsing Lee ,  Huey-Liang Hwang

IPC: H01L218234

CPC classification number: H01L27/027 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An ESD protection structure that when connected between an input/output pad on a semiconductor substrate and a reference voltage source, will protect internal circuits formed on the semiconductor substrate from over stress due to excessively high voltages of an ESD voltage source. The ESD protection structure has a uniform discharge current to prevent damage to the ESD protection device thus allowing increased protection to the internal circuits. The ESD protection device has at least one source region that is the emitters of parasitic transistors connected to the reference voltage source and at least one drain region that is the collectors of the parasitic transistors connected to the junction of the input/output pad and the internal circuitry. The ESD protection device further has at least one gate electrode formed above a channel region. The channel region is the region is between each of the source regions and the drain regions. The gate electrodes are connected to the reference voltage source. Each gate electrode has a variable length and thus the channel region has a variable length. The channel region is the base of the parasitic transistors formed by the ESD protection structure. The variable length of the channel region and thus the base of the parasitic transistors create an ESD current that is distributed uniformly over said ESD protection structure.

Abstract translation: 当连接在半导体衬底上的输入/输出焊盘与参考电压源之间时，ESD保护结构将保护由于ESD电压源的过高电压而在半导体衬底上形成的内部电路免受过度应力。 ESD保护结构具有均匀的放电电流，以防止ESD保护器件的损坏，从而允许增加对内部电路的保护。 ESD保护器件具有至少一个源极区域，其是连接到参考电压源的寄生晶体管的发射极，以及连接到输入/输出焊盘和内部的结的寄生晶体管的集电极的至少一个漏极区域 电路。 ESD保护器件还具有形成在通道区域上方的至少一个栅电极。 沟道区域是在源极区域和漏极区域中的每一个之间的区域。 栅电极连接到参考电压源。 每个栅电极具有可变长度，因此沟道区具有可变长度。 通道区域是由ESD保护结构形成的寄生晶体管的基极。 沟道区域的可变长度以及寄生晶体管的基极产生均匀分布在所述ESD保护结构上的ESD电流。

公开(公告)号：US06232160B1

公开(公告)日：2001-05-15

申请号：US09396515

申请日：1999-09-15

Applicant: Jiaw-Ren Shih ,  Shui-Hung Chen ,  Jian-Hsing Lee

Inventor： Jiaw-Ren Shih ,  Shui-Hung Chen ,  Jian-Hsing Lee

IPC: H01L21336

CPC classification number: H01L29/66537 ,  H01L29/1045 ,  H01L29/66553 ,  H01L29/6659

Abstract: A new method of suppressing short channel effect without increasing junction leakage and capacitance using a single self-aligning delta-channel implant is described. A pad oxide layer is formed over a semiconductor substrate. A silicon nitride layer is deposited overlying the pad oxide layer and patterned to leave an opening where a gate electrode will be formed. Dielectric spacers are formed on the sidewalls of the opening wherein a portion of the substrate is not covered by the spacers within the opening. A single delta-channel implant is made into the semiconductor substrate using the silicon nitride layer and the dielectric spacers as a mask. This delta-channel implant suppresses short channel effect without increasing junction leakage and capacitance. The dielectric spacers are removed. A polysilicon layer is deposited over the silicon nitride layer and within the opening and polished to leave the polysilicon layer only within the opening. The silicon nitride layer is removed to form a gate electrode wherein the delta-channel implant underlies the gate electrode. Thereafter, lightly doped regions and source and drain regions are formed within the semiconductor substrate associated with the gate electrode to complete fabrication of the integrated circuit device.

Abstract translation: 描述了使用单个自对准delta通道植入物抑制短通道效应而不增加结漏电和电容的新方法。 衬垫氧化物层形成在半导体衬底上。 将氮化硅层沉积在衬垫氧化物层上并被图案化以留下将形成栅电极的开口。 电介质间隔物形成在开口的侧壁上，其中衬底的一部分未被开口内的间隔物覆盖。 使用氮化硅层和电介质间隔物作为掩模将单个Δ沟道注入制成半导体衬底。 该delta通道注入抑制短沟道效应，而不增加结漏电流。 去除电介质垫片。 多晶硅层沉积在氮化硅层之上并且在开口内被抛光，仅在开口内离开多晶硅层。 去除氮化硅层以形成栅电极，其中该三角沟道注入位于该栅电极下方。 此后，在与栅极电极相关联的半导体衬底内形成轻掺杂区域和源极和漏极区域，以完成集成电路器件的制造。

公开(公告)号：US06207482B1

公开(公告)日：2001-03-27

申请号：US09346528

申请日：1999-07-02

Applicant: Jiaw-Ren Shih ,  Shui-Hung Chen ,  Jian-Hsing Lee ,  Chia-Hung Tunga

Inventor： Jiaw-Ren Shih ,  Shui-Hung Chen ,  Jian-Hsing Lee ,  Chia-Hung Tunga

IPC: H01L218238

CPC classification number: H01L29/66537 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823842

Abstract: The invention provides a gate pocket implantation and post-processing sequence that allows for the creation of a deep and narrow pocket implant without affecting gate threshold voltage and the integrity of the gate oxide layer.

Abstract translation: 本发明提供了一种门口注入和后处理顺序，其允许创建深而窄的口袋注入而不影响栅极阈值电压和栅极氧化物层的完整性。