公开(公告)号：US06756642B2

公开(公告)日：2004-06-29

申请号：US10291053

申请日：2002-11-07

申请人： Jian-Hsing Lee ,  Ta-Lee Yu ,  Shui-Hung Chen

发明人： Jian-Hsing Lee ,  Ta-Lee Yu ,  Shui-Hung Chen

IPC分类号： H01L2362

CPC分类号： H01L27/0262 ,  H01L29/87

摘要： In a high voltage n-channel MOS structure, inserting p+ diffusion and an n-well into NMOS drain area, along with providing ESD protection by means of forming parasitic SCR, allows using signal of 5V and decreases snapback voltage below 2V.

摘要翻译： 在高电压n沟道MOS结构中，将p +扩散和n阱插入NMOS漏极区域，并通过形成寄生SCR提供ESD保护，允许使用5V信号，并将回跳电压降低到2V以下。

公开(公告)号：US06703663B1

公开(公告)日：2004-03-09

申请号：US09655086

申请日：2000-09-05

申请人： Jian-Hsing Lee ,  Yi-Hsun Wu ,  Jian-Ren Shih

发明人： Jian-Hsing Lee ,  Yi-Hsun Wu ,  Jian-Ren Shih

IPC分类号： H01L2976

CPC分类号： H01L29/7833 ,  H01L21/823814 ,  H01L27/0266 ,  H01L29/1083

摘要： A method of forming a semiconductor memory device formed on a semiconductor substrate with an N-well and a P-well comprises the following steps. Form over a substrate the combination of a gate oxide layer and a gate layer patterned into gate stacks with sidewalls for an NMOS FET device over a P-well in the substrate and a PMOS FET device over an N-well. Form P− lightly doped S/D regions in the N-well and N− lightly doped S/D regions in the P-well. Form spacers on the sidewalls of the gate stacks. Thereafter form deep N− lightly doped S/D regions in the P-well, and form deep P− lightly doped S/D regions in the N-well. Form heavily doped P++ regions self-aligned with the gate below future P+ S/D sites to be formed self-aligned with the spacers in the N-well, and form heavily doped N++ regions self-aligned with the gate below future N+ S/D sites to be formed self-aligned with the spacers in the P-well.

摘要翻译： 用N阱和P阱形成在半导体衬底上的半导体存储器件的形成方法包括以下步骤。 在衬底上形成栅极氧化物层和栅极层的组合，栅极层与衬底中的P阱上的NMOS FET器件的侧壁和N阱上的PMOS FET器件构图成栅极堆叠。 在P阱中的N阱和N-轻掺杂的S / D区中形成P-轻掺杂的S / D区。 在栅极堆叠的侧壁上形成间隔物。 然后在P阱中形成深N轻掺杂的S / D区，并在N阱中形成深P-轻掺杂的S / D区。 形成与未来P + S / D位置下方的栅极自对准的重掺杂P ++区域，以与N阱中的间隔物自对准，并形成与未来N + S / D的栅极自对准的重掺杂N ++区域， D点与P阱中的间隔物自对准。

公开(公告)号：US06682993B1

公开(公告)日：2004-01-27

申请号：US10161007

申请日：2002-05-31

申请人： Yi-Hsun Wu ,  Jian-Hsing Lee

发明人： Yi-Hsun Wu ,  Jian-Hsing Lee

IPC分类号： H01L2104

CPC分类号： H01L27/0266

摘要： The invention consists of an ESD protection discharging NMOS with a special drain dopant region that enables a lower voltage trigger point for Vcc to Vss ESD power protection. To enable this ESD protection, the NMOS source connected to a first voltage bus line, or Vcc, and the drain is connected to a second voltage bus line, or ground. The NMOS device gate is connected to ground through a difflused resistor assuring the device remains in an off state during normal operation. The unique invention special dopant region is located under and around the NMOS drain which lowers the drain to substrate breakdown voltage enabling the ESD protection current discharge to start at a lower voltage than otherwise. This feature reduces voltage stress on the gates of active devices being protected, and enables higher ESD current discharges at the same power level as for devices without the special drain dopant region.

摘要翻译： 本发明包括具有特殊漏极掺杂剂区域的ESD保护放电NMOS，其能够实现用于Vcc至Vss ESD功率保护的较低电压触发点。 为了实现该ESD保护，连接到第一电压总线或Vcc的NMOS源和漏极连接到第二电压总线或地。 NMOS器件栅极通过差分电阻器连接到地，确保器件在正常工作期间保持关断状态。 独特的发明特殊掺杂剂区域位于NMOS漏极的下面和周围，这降低了漏极到衬底的击穿电压，使得ESD保护电流放电能够以比其他电压更低的电压开始。 该特性降低了受保护的有源器件的栅极上的电压应力，并且能够实现与没有特殊漏极掺杂剂区域的器件相同功率电平的更高的ESD电流放电。

公开(公告)号：US06645820B1

公开(公告)日：2003-11-11

申请号：US10119337

申请日：2002-04-09

申请人： Kuo Reay Peng ,  Jian-Hsing Lee ,  Shui-Hung Chen

发明人： Kuo Reay Peng ,  Jian-Hsing Lee ,  Shui-Hung Chen

IPC分类号： H01L21331

CPC分类号： H01L29/861 ,  H01L27/0255 ,  Y10S438/979 ,  Y10S438/983

摘要： An ESD protection circuit protects integrated circuits having multiple power supply voltage sources from damage when an ESD event causes excessive differential voltages between the multiple separate power supply voltage sources. The ESD protection circuit has a string of serially connected lateral polycrystalline silicon diodes characterized by consistent turn-on threshold voltage level such that as the number of stage of the ESD protection circuit increase, the turn-on voltage threshold of the ESD protection circuit increase linearly.

摘要翻译： 当ESD事件在多个单独的电源电压源之间引起过大的差分电压时，ESD保护电路保护具有多个电源电压源的集成电路免受损坏。 ESD保护电路具有一串串联连接的横向多晶硅二极管，其特征在于一致的开启阈值电压电平，使得随着ESD保护电路的级数增加，ESD保护电路的导通电压阈值线性增加 。

公开(公告)号：US06492208B1

公开(公告)日：2002-12-10

申请号：US09671214

申请日：2000-09-28

申请人： Tao Cheng ,  Jian-Hsing Lee

发明人： Tao Cheng ,  Jian-Hsing Lee

IPC分类号： H01L21332

CPC分类号： H01L27/0262

摘要： An embedded parasitic silicon controlled rectifier (SCR) in conjunction with a Gated-NMOS is created for protecting a chip input or output pad from electrostatic discharge ESD, by inserting a p+ diffusion and the n-well in the drain side and a part of the drain to forms a low-trigger, high efficiency SCR. The device layout is such that the drain connection is tightly tied together at the p+ diffusion and the n+ drain making that connection very short and, thereby, preventing latch-up. The parasitic SCR is contained entirely within the n+ diffusion (the source of the grounded gate NMOS transistor) at either side of the structure and, therefore, called an embedded SCR. For a 12 volt I/O device each of two n+ drains is placed in its own n-type doped drain (ndd) area straddling halfway the n-well. The structure is repeated as required and a p+ diffusion is implanted at both perimeters and connected to the nearest n+ source and a reference voltage.

摘要翻译： 通过在漏极侧插入p +扩散和n阱，创建了一个与门极NMOS相结合的嵌入式寄生可控硅整流器（SCR），用于保护芯片输入或输出焊盘免受静电放电ESD的影响。 漏极形成低触发，高效SCR。 器件布局使得漏极连接在p +扩散和n +漏极紧密连接在一起，使得该连接非常短，从而防止闩锁。 寄生SCR完全包含在结构两侧的n +扩散（接地栅极NMOS晶体管的源极）内，因此被称为嵌入式SCR。 对于12伏I / O设备，两个n +漏极中的每一个都放置在跨越n-阱一半的其自身的n型掺杂漏极（ndd）区域中。 根据需要重复该结构，并且在两个周边注入p +扩散并连接到最近的n +源和参考电压。

公开(公告)号：US06459127B1

公开(公告)日：2002-10-01

申请号：US10043793

申请日：2002-01-14

申请人： Jian-Hsing Lee ,  Kuo-Chio Liu ,  Bing-Lung Liao ,  Jiaw-Ren Shih

发明人： Jian-Hsing Lee ,  Kuo-Chio Liu ,  Bing-Lung Liao ,  Jiaw-Ren Shih

IPC分类号： H01L2362

CPC分类号： H01L27/0266

摘要： NMOS transistors for a high voltage process are protected from electrostatic discharge (ESD) by parasitic SCRs, where the two NMOS transistors and the two SCRs are designed to be in a completely symmetrical arrangement so that the currents in the components of the SCRs are completely uniform. This symmetry is achieved by adding a p+ diffusion to the source of one of the NMOS transistors. The added p+ diffusion guarantees that the resistance seen by both SCRs is identical. This insures even current distribution between both SCRs and thereby improves the high voltage characteristics of the ESD device.

摘要翻译： 用于高电压工艺的NMOS晶体管通过寄生SCR防止静电放电（ESD），其中两个NMOS晶体管和两个SCR被设计为完全对称的布置，使得SCR的部件中的电流是完全均匀的 。 该对称性是通过向NMOS晶体管之一的源极添加p +扩散来实现的。 添加的p +扩散保证两个SCR看到的电阻是相同的。 这确保了两个SCR之间的均匀电流分布，从而改善了ESD器件的高电压特性。

公开(公告)号：US06437408B1

公开(公告)日：2002-08-20

申请号：US09904146

申请日：2001-07-13

申请人： Jiaw-Ren Shih ,  Shui-Hung Shen ,  Jian-Hsing Lee ,  Chrong Jung Lin

发明人： Jiaw-Ren Shih ,  Shui-Hung Shen ,  Jian-Hsing Lee ,  Chrong Jung Lin

IPC分类号： H01L2100

CPC分类号： H01L21/28123

摘要： A plasma damage protection cell using floating N/P/N and P/N/P structure, and a method to form the same are disclosed. Floating structures of the protection cell and the floating gates for the MOS devices are formed simultaneously on a semiconductor substrate having shallow trench isolation. The floating structures are implanted separately to form the N/P/N and P/N/P bipolar base, emitter and collector regions while the source/drain of the respective NMOS and PMOS devices are implanted with appropriate sequencing. The floating structures are connected to the substrate with appropriate polarity to provide protection at low leakage current levels and with tunable punch-through voltages.

摘要翻译： 公开了使用浮动N / P / N和P / N / P结构的等离子体损伤保护单元及其形成方法。 保护电池的浮动结构和用于MOS器件的浮置栅极同时形成在具有浅沟槽隔离的半导体衬底上。 分别注入浮动结构以形成N / P / N和P / N / P双极基极，发射极和集电极区域，同时以适当的顺序植入各个NMOS和PMOS器件的源极/漏极。 浮动结构以适当的极性连接到基板，以在低泄漏电流水平和可调穿通电压下提供保护。

公开(公告)号：US06323523B1

公开(公告)日：2001-11-27

申请号：US09494682

申请日：2000-01-31

申请人： Jian-Hsing Lee ,  Yi-Hsun Wu ,  Shui-Hung Chen ,  Jiaw-Ren Shih

发明人： Jian-Hsing Lee ,  Yi-Hsun Wu ,  Shui-Hung Chen ,  Jiaw-Ren Shih

IPC分类号： H01L2362

CPC分类号： H01L27/0262 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ESD protective circuit formed by n-type pull-up transistors and n-type pull-down transistors on a p-type silicon substrate for protecting an internal device circuit is disclosed. In the circuit, a n-well region having a p+ diffusion and a n+ diffusion therein being formed adjacent one drain region of one pull-up transistors, the p+ diffusion and a n+ diffusion, as well as all the drain regions of the pull-up transistors are coupled to a power supply. All the source regions of the pull-up transistors and drain regions of the pull-down transistors are connected to an I/O pad. All the source regions of the pull-down transistors including the p+ guardings are grounded. The gates of all transistors are connected to the internal device circuit so that the internal device circuit will be immunity from the ESD.

摘要翻译： 公开了一种用于保护内部器件电路的p型硅衬底上的n型上拉晶体管和n型下拉晶体管形成的ESD保护电路。 在该电路中，在一个上拉晶体管的一个漏极区附近形成有p +扩散和n +扩散的n阱区，p +扩散和n +扩散以及所述漏极区的所有漏极区， 上拉晶体管耦合到电源。 下拉晶体管的上拉晶体管和漏极区域的所有源极区域都连接到I / O焊盘。 包括p +保护的下拉晶体管的所有源极区域接地。 所有晶体管的栅极连接到内部器件电路，使得内部器件电路将免受ESD的影响。

公开(公告)号：US06277723B1

公开(公告)日：2001-08-21

申请号：US09418030

申请日：1999-10-14

申请人： Jiaw-Ren Shih ,  Shui-Hung Chen ,  Jian-Hsing Lee ,  Chrong Jung Lin

发明人： Jiaw-Ren Shih ,  Shui-Hung Chen ,  Jian-Hsing Lee ,  Chrong Jung Lin

IPC分类号： H01L2144

CPC分类号： H01L21/28123

摘要： A plasma damage protection cell using floating N/P/N and P/N/P structure, and a method to form the same are disclosed. Floating structures of the protection cell and the floating gates for the MOS devices are formed simultaneously on a semiconductor substrate having shallow trench isolation. The floating structures are implanted separately to form the N/P/N and P/N/P bipolar base, emitter and collector regions while the source/drain of the respective NMOS and PMOS devices are implanted with appropriate sequencing. The floating structures are connected to the substrate with appropriate polarity to provide protection at low leakage current levels and with tunable punch-through voltages.

摘要翻译： 公开了使用浮动N / P / N和P / N / P结构的等离子体损伤保护单元及其形成方法。 保护电池的浮动结构和用于MOS器件的浮置栅极同时形成在具有浅沟槽隔离的半导体衬底上。 分别注入浮动结构以形成N / P / N和P / N / P双极基极，发射极和集电极区域，同时以适当的顺序植入各个NMOS和PMOS器件的源极/漏极。 浮动结构以适当的极性连接到基板，以在低泄漏电流水平和可调穿通电压下提供保护。

公开(公告)号：US06246075B1

公开(公告)日：2001-06-12

申请号：US09507883

申请日：2000-02-22

申请人： Hung-Der Su ,  Jian-Hsing Lee ,  Di-Son Kuo

发明人： Hung-Der Su ,  Jian-Hsing Lee ,  Di-Son Kuo

IPC分类号： H01L2358

CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ensemble of test structures comprising arrays of polysilicon plate MOS capacitors for the measurement of electrical quality of the MOSFET gate insulation is described. The test structures also measure plasma damage to these gate insulators incurred during metal etching and plasma ashing of photoresist. The structures are formed, either on test wafers or in designated areas of wafers containing integrated circuit chips. One of the test structures is designed primarily to minimize plasma damage so that oxide quality, and defect densities may be measured unhampered by interface traps created by plasma exposure. Other structures provide different antenna-to-oxide area ratios, useful for assessing plasma induced oxide damage and breakdown. The current-voltage characteristics of the MOS capacitors are measured by probing the structures on the wafer, thereby providing timely process monitoring capability.

摘要翻译： 描述了包括用于测量MOSFET栅极绝缘的电气质量的多晶硅板MOS电容器阵列的测试结构的集合。 测试结构还测量在金属蚀刻和光致抗蚀剂的等离子体灰化期间引起的这些栅绝缘体的等离子体损伤。 在测试晶片上或在包含集成电路芯片的晶片的指定区域中形成结构。 其中一个测试结构主要设计为最小化等离子体损伤，从而可以通过等离子体曝光产生的界面陷阱来测量氧化物质量和缺陷密度。 其他结构提供不同的天线到氧化物面积比，可用于评估等离子体诱导的氧化物损伤和击穿。 通过探测晶片上的结构来测量MOS电容器的电流 - 电压特性，从而提供及时的过程监控能力。