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公开(公告)号：US07821053B2
公开(公告)日：2010-10-26
申请号：US11560126
申请日：2006-11-15
IPC分类号： H01L29/93
CPC分类号： H01L29/94
摘要： Disclosed are embodiments of a transistor that operates as a capacitor and an associated method of tuning capacitance within such a capacitor. The embodiments of the capacitor comprise a field effect transistor with front and back gates above and below a semiconductor layer, respectively. The capacitance value exhibited by the capacitor can be selectively varied between two different values by changing the voltage condition in a source/drain region of the transistor, e.g., using a switch or resistor between the source/drain region and a voltage supply. Alternatively, the capacitance value exhibited by the capacitor can be selectively varied between multiple different values by changing voltage conditions in one or more of multiple channel regions that are flanked by multiple source/drain regions within the transistor. The capacitor will exhibit different capacitance values depending upon the conductivity in each of the channel regions.
摘要翻译： 公开了用作电容器的晶体管的实施例以及在这种电容器内调谐电容的相关联的方法。 电容器的实施例包括分别在半导体层上方和下方具有前栅极和后栅极的场效应晶体管。 通过改变晶体管的源极/漏极区域中的电压条件，例如使用源极/漏极区域和电压源之间的开关或电阻器，可以通过改变晶体管的源极/ 或者，可以通过改变在晶体管内侧面有多个源极/漏极区域的多个沟道区域中的一个或多个中的电压条件来选择性地在多个不同值之间变化由电容器呈现的电容值。 根据每个通道区域中的电导率，电容器将呈现不同的电容值。
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82.发明授权公开(公告)号：US07729159B2
公开(公告)日：2010-06-01
申请号：US12146554
申请日：2008-06-26
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： A static random access memory (SRAM) device a pair of cross-coupled, complementary metal oxide semiconductor (CMOS) inverters configured as a storage cell for a bit of data, a first pair of transfer gates configured to couple complementary internal nodes of the storage cell to a corresponding pair of bitlines during a read operation of the device; and a second pair of transfer gates configured to couple the storage cell nodes to the pair of bitlines during a write operation of the device, wherein impedance between the bitlines and the storage cell nodes during the write operation is less than that for the read operation, wherein impedance between the bitlines and the storage cell nodes during the write operation is less than that for the read operation.
摘要翻译： 一种静态随机存取存储器（SRAM）装置，被配置为用于数据位的存储单元的一对交叉耦合的互补金属氧化物半导体（CMOS）反相器，第一对传输门，被配置为耦合所述存储器的互补的内部节点 在设备的读取操作期间，单元到相应的位线对; 以及第二对传输门，其被配置为在所述器件的写入操作期间将所述存储单元节点耦合到所述一对位线，其中在所述写入操作期间所述位线和所述存储单元节点之间的阻抗小于所述读操作的阻抗， 其中在写入操作期间位线和存储单元节点之间的阻抗小于读取操作的阻抗。
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公开(公告)号：US07705626B2
公开(公告)日：2010-04-27
申请号：US11847362
申请日：2007-08-30
申请人： Igor Arsovski , Joseph A. Iadanza
发明人： Igor Arsovski , Joseph A. Iadanza
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/00346 , H03K17/162
摘要： A design structure for eliminating step response power supply perturbation during voltage island power-up/power-down on an integrated circuit is disclosed. An IC chip communicates with a primary power supply and includes at least one voltage island. A primary header on the voltage island of the chip communicates with the primary power supply via a primary header power path. A secondary header on the voltage island of the chip communicates with a secondary power supply via a secondary header power path. A control decoder communicating with the IC chip and the voltage island regulates the state of the primary and secondary headers.
摘要翻译： 公开了一种用于在集成电路上的电压岛上电/掉电期间消除阶跃响应电源扰动的设计结构。 IC芯片与主电源通信并且包括至少一个电压岛。 芯片的电压岛上的主要头部通过主头电源路径与主电源通信。 芯片的电压岛上的次级标题通过辅助电源通路与二次电源通信。 与IC芯片和电压岛通信的控制解码器调节主集线器和副集线器的状态。
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84.发明申请Detection Method for Identifying Unintentionally Forward-Biased Diode Devices in an Integrated Circuit Device Design 失效用于在集成电路器件设计中识别无意的前向偏置二极管器件的检测方法公开(公告)号：US20090089724A1
公开(公告)日：2009-04-02
申请号：US11862887
申请日：2007-09-27
IPC分类号： G06F17/50
CPC分类号： G06F17/504 , G06F17/5045
摘要： A detection method for identifying unintentionally forward-biased diode devices identifies one or more forward-biased diodes directly from a graphical representation of an integrated circuit (IC) device design. The graphical representation describing one or more IC components as a plurality of geometric shapes that correspond to a set of patterns in at least one semiconductor layer. A detection method may work in conjunction with one or more checks (e.g., electrical rule check (ERC)) to analyze the graphical representation and ensure its manufacturability by reducing the likelihood the forward-biased diodes will be present in the manufactured IC device.
摘要翻译： 用于识别无意的正向偏置的二极管器件的检测方法从集成电路（IC）器件设计的图形表示直接识别一个或多个正向偏置二极管。 将一个或多个IC组件描述为对应于至少一个半导体层中的一组图案的多个几何形状的图形表示。 检测方法可以与一个或多个检查（例如，电气规则检查（ERC））一起工作以分析图形表示，并通过降低正向偏置二极管将存在于制造的IC器件中的可能性来确保其可制造性。
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公开(公告)号：US07511528B2
公开(公告)日：2009-03-31
申请号：US11461788
申请日：2006-08-02
申请人： Igor Arsovski , Joseph A. Iadanza
发明人： Igor Arsovski , Joseph A. Iadanza
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/00346
摘要： A system and method for eliminating step response power supply perturbation during voltage island power-up/power-down on an integrated circuit is disclosed. An IC chip communicates with a primary power supply and includes at least one voltage island. A primary header on the voltage island of the chip communicates with the primary power supply via a primary header power path. A secondary header on the voltage island of the chip communicates with a secondary power supply via a secondary header power path. A control decoder communicating with the IC chip and the voltage island regulates the state of the primary and secondary headers.
摘要翻译： 公开了一种用于在集成电路上的电压岛上电/掉电期间消除阶跃响应电源扰动的系统和方法。 IC芯片与主电源通信并且包括至少一个电压岛。 芯片的电压岛上的主要头部通过主头电源路径与主电源通信。 芯片的电压岛上的次级标题通过辅助电源通路与二次电源通信。 与IC芯片和电压岛通信的控制解码器调节主集线器和副集线器的状态。
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86.发明申请公开(公告)号：US20090033395A1
公开(公告)日：2009-02-05
申请号：US11833538
申请日：2007-08-03
CPC分类号： H01L27/0705 , H01L21/823418
摘要： Disclosed are embodiments of a variable-delay field effect transistor (FET) having multiple source regions that can be individually and selectively biased to provide an electrical connection to a single drain region. Delay is a function of which of the multiple source regions is/are selectively biased as well as a function of gate resistance and capacitance. Such a variable-delay FET can be incorporated into a phase adjusting circuit, which uses gate propagation delays to selectively phase adjust an input signal. The phase adjusting circuit can be tuned by incorporating non-salicided resistances and additional capacitance at various positions on the gate structure. The phase adjusting circuit can further be modified into a phase adjusting mixer circuit that enables a phase adjusted signal to be combined with an additional signal.
摘要翻译： 公开了具有多个源极区域的可变延迟场效应晶体管（FET）的实施例，其可被单独和选择性地偏置以提供到单个漏极区域的电连接。 延迟是多个源极区域中的哪一个被选择性偏置以及栅极电阻和电容的函数的函数。 这样的可变延迟FET可以并入相位调整电路中，该相位调整电路使用栅极传播延迟来选择性地相位调整输入信号。 相位调整电路可以通过在栅极结构上的各个位置并入非水银电阻和附加电容来调节。 相位调整电路可以进一步修改为使相位调整信号与附加信号组合的相位调整混频器电路。
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87.发明申请MICRO-PHASE ADJUSTING AND MICRO-PHASE ADJUSTING MIXER CIRCUITS DESIGNED WITH STANDARD FIELD EFFECT TRANSISTOR STRUCTURES 审中-公开具有标准场效应晶体管结构的微相调节和微相调节混频器电路公开(公告)号：US20090033389A1
公开(公告)日：2009-02-05
申请号：US11833567
申请日：2007-08-03
CPC分类号： H03K5/06 , H03K2005/00052 , H03K2005/00058
摘要： Disclosed herein are embodiments of a programmable phase adjusting circuit, a programmable phase adjusting mixer circuit and design structures for these circuits. These circuits comprise a variable delay device connected between input and output nodes. The device includes multiple FETs with input diffusion regions that are connected to a voltage rail via switches so that they can be selectively biased, gates that are connected in series to the input node so that a periodic input signal can be propagated sequentially through each of the gates and output diffusion regions that are connected in parallel to the output node. A current source is connected between the output node and another voltage rail for biasing the output node when the variable delay device is off. The variable delay device enables a circuit in which small increments of selectable phase adjustments can be made to the periodic input signal as a function of propagation delay.
摘要翻译： 这里公开了可编程相位调整电路，可编程相位调整混频器电路和这些电路的设计结构的实施例。 这些电路包括连接在输入和输出节点之间的可变延迟器件。 该器件包括多个FET，其输入扩散区通过开关连接到电压轨，使得它们可以被选择性偏置，与输入节点串联连接的栅极，使得周期性输入信号可以顺序地传播通过 门和输出扩散区域并联连接到输出节点。 当可变延迟装置关闭时，电流源连接在输出节点和另一个电压轨道之间，用于偏置输出节点。 可变延迟装置使得能够作为传播延迟的函数对周期性输入信号进行可选相位调整的小增量的电路。
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88.发明申请DESIGN STRUCTURE FOR IMPROVED SRAM DEVICE PERFORMANCE THROUGH DOUBLE GATE TOPOLOGY 审中-公开通过双门拓扑改进SRAM设备性能的设计结构公开(公告)号：US20080273366A1
公开(公告)日：2008-11-06
申请号：US11851408
申请日：2007-09-07
IPC分类号： G11C5/06
CPC分类号： G11C11/412 , G11C11/413
摘要： A design structure embodied in a machine readable medium used in a design process includes a static random access memory (SRAM) device having a pair of cross-coupled, complementary metal oxide semiconductor (CMOS) inverters configured as a storage cell for a bit of data, a first pair of transfer gates configured to couple complementary internal nodes of the storage cell to a corresponding pair of bitlines during a read operation of the device; and a second pair of transfer gates configured to couple the storage cell nodes to the pair of bitlines during a write operation of the device, wherein impedance between the bitlines and the storage cell nodes during the write operation is less than that for the read operation, wherein impedance between the bitlines and the storage cell nodes during the write operation is less than that for the read operation.
摘要翻译： 体现在设计过程中使用的机器可读介质中的设计结构包括具有一对交叉耦合的互补金属氧化物半导体（CMOS）逆变器的静态随机存取存储器（SRAM）器件，其被配置为用于数据位的存储单元 配置为在所述设备的读取操作期间将所述存储单元的互补内部节点耦合到对应的位线对的第一对传输门; 以及第二对传输门，其被配置为在所述器件的写入操作期间将所述存储单元节点耦合到所述一对位线，其中在所述写入操作期间所述位线和所述存储单元节点之间的阻抗小于所述读操作的阻抗， 其中在写入操作期间位线和存储单元节点之间的阻抗小于读取操作的阻抗。
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公开(公告)号：US20080030223A1
公开(公告)日：2008-02-07
申请号：US11461788
申请日：2006-08-02
申请人： Igor Arsovski , Joseph A. Iadanza
发明人： Igor Arsovski , Joseph A. Iadanza
IPC分类号： H03K19/173
CPC分类号： H03K19/00346
摘要： A system and method for eliminating step response power supply perturbation during voltage island power-up/power-down on an integrated circuit is disclosed. An IC chip communicates with a primary power supply and includes at least one voltage island. A primary header on the voltage island of the chip communicates with the primary power supply via a primary header power path. A secondary header on the voltage island of the chip communicates with a secondary power supply via a secondary header power path. A control decoder communicating with the IC chip and the voltage island regulates the state of the primary and secondary headers.
摘要翻译： 公开了一种用于在集成电路上的电压岛上电/掉电期间消除阶跃响应电源扰动的系统和方法。 IC芯片与主电源通信并且包括至少一个电压岛。 芯片的电压岛上的主要头部通过主头电源路径与主电源通信。 芯片的电压岛上的次级标题通过辅助电源通路与二次电源通信。 与IC芯片和电压岛通信的控制解码器调节主集线器和副集线器的状态。
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90.发明授权Structure and method for providing gate leakage isolation locally within analog circuits 失效在模拟电路中局部提供栅极泄漏隔离的结构和方法公开(公告)号：US07268632B2
公开(公告)日：2007-09-11
申请号：US11163013
申请日：2005-09-30
CPC分类号： H03L7/093 , H03L7/0891
摘要： A loop filter for a phase-locked-loop is provided, comprising a set of capacitor banks coupled in parallel to form the loop filter, and a detection circuit for identifying and isolating defective capacitor banks. A method for providing a loop filter for a phase-locked-loop in accordance with an embodiment of the present invention includes the steps of forming the loop filter using a set of capacitor banks coupled in parallel, detecting any defective capacitor banks in the set of capacitor banks, isolating each defective capacitor bank, providing a set of redundant capacitor banks, and replacing each defective capacitor bank with a redundant capacitor bank from the set of redundant capacitor banks.
摘要翻译： 提供了一种用于锁相环的环路滤波器，包括并联耦合以形成环路滤波器的一组电容器组，以及用于识别和隔离有缺陷的电容器组的检测电路。 根据本发明实施例的用于提供用于锁相环的环路滤波器的方法包括以下步骤：使用并联耦合的一组电容器组形成环路滤波器，检测该组中的任何有缺陷的电容器组 电容器组，隔离每个有缺陷的电容器组，提供一组冗余电容器组，并从冗余电容器组组中的冗余电容器组替换每个有缺陷的电容器组。
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