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    Semiconductor integrated circuit device
    81.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US07612601B2

    公开(公告)日：2009-11-03

    申请号：US11783920

    申请日：2007-04-13

    申请人： Hiroyuki Mizuno ,  Yusuke Kanno ,  Kazumasa Yanagisawa ,  Yohihiko Yasu ,  Nobuhiro Oodaira

    发明人： Hiroyuki Mizuno ,  Yusuke Kanno ,  Kazumasa Yanagisawa ,  Yohihiko Yasu ,  Nobuhiro Oodaira

    IPC分类号： H03L5/00

    CPC分类号： H03K19/0016 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0928 ,  H01L27/11898 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.

    摘要翻译： 具有第一电路块BLK1，第二电路块DRV1和用于将第一电路块连接到第二电路块的转换电路MIO1的半导体集成电路器件。 第一电路块包括用于施加电源电压的第一模式和用于关断电源电压的第二模式。 转换电路具有将第二电路块的输入节点的电位维持在操作电位的功能，从而当第一电路块处于第二模式时抑制穿透电流流动。 转换电路（MIO1〜MIO4）通常用于连接电路块。

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    82.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
    半导体集成电路设备

    公开(公告)号：US20080114967A1

    公开(公告)日：2008-05-15

    申请号：US11935790

    申请日：2007-11-06

    申请人： Makoto Saen ,  Kenichi Osada ,  Tetsuya Yamada ,  Yusuke Kanno ,  Satoshi Misaka

    发明人： Makoto Saen ,  Kenichi Osada ,  Tetsuya Yamada ,  Yusuke Kanno ,  Satoshi Misaka

    IPC分类号： G06F9/302

    CPC分类号： G06F1/3228 ,  H01L2924/0002 ,  H01L2924/00

    摘要： There is provided a semiconductor integrated circuit device which consumes less power and enables real-time processing. The semiconductor integrated circuit device comprises: thermal sensors which can detect temperature, determine whether the detection result exceeds each of the above reference values and output the result; and a control block capable of controlling the operations of arithmetic blocks based on the output signals of the thermal sensors, wherein the control block returns to an operation state from a suspended state with an interrupt signal based on the output signals of the thermal sensors and determines the operation conditions of the arithmetic blocks to ensure that the temperature conditions of the arithmetic blocks are satisfied. Thereby, power consumption is reduced and real-time processing efficiency is improved.

    摘要翻译： 提供了一种半导体集成电路器件，其消耗较少功率并实现实时处理。 半导体集成电路装置包括：可以检测温度的热传感器，确定检测结果是否超过上述参考值，并输出结果; 以及控制块，其能够基于所述热传感器的输出信号来控制运算块的运算，其中，所述控制块基于所述热传感器的输出信号，利用中断信号从暂停状态返回到运行状态，并且确定 运算块的操作条件，以确保运算块的温度条件得到满足。 从而降低了功耗，提高了实时处理效率。

    Semiconductor intergrated circuit and data processing system
    84.
    发明申请
    Semiconductor intergrated circuit and data processing system 有权
    半导体集成电路和数据处理系统

    公开(公告)号：US20070101088A1

    公开(公告)日：2007-05-03

    申请号：US11641808

    申请日：2006-12-20

    申请人： Kazushige Ayukawa ,  Seiji Miura ,  Jun Satoh ,  Takao Watanabe ,  Kazumasa Yanagisawa ,  Yusuke Kanno ,  Hiroyuki Mizuno

    发明人： Kazushige Ayukawa ,  Seiji Miura ,  Jun Satoh ,  Takao Watanabe ,  Kazumasa Yanagisawa ,  Yusuke Kanno ,  Hiroyuki Mizuno

    IPC分类号： G06F13/00

    CPC分类号： G11C7/1006 ,  G06F12/0215 ,  G06F12/0893 ,  G06F13/161 ,  G06F2212/3042 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/4093 ,  G11C2207/104 ,  G11C2207/2245

    摘要： To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.

    摘要翻译： 为了提高第一次访问的速度（从先前访问的字线读取访问）到多存储体存储器，使用多存储体存储器宏结构。 数据保存在每个存储体的读出放大器中。 当对保持的数据进行访问时，输出由读出放大器锁存的数据，从而提高对存储器宏结构的首次访问的速度。 即，使每个存储体用作读出放大器高速缓存。 为了更好地提高这种感测放大器高速缓存的命中率，访问控制器在访问存储器宏结构之后自我预取下一个地址（已经添加了预定偏移量的地址），以便自我预取中的数据 地址由另一个存储体中的读出放大器预读。

    Information processing apparatus using index and TAG addresses for cache
    86.
    发明授权
    Information processing apparatus using index and TAG addresses for cache 失效
    信息处理设备使用索引和TAG地址进行缓存

    公开(公告)号：US07159067B2

    公开(公告)日：2007-01-02

    申请号：US10702482

    申请日：2003-11-07

    申请人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Takao Watanabe

    发明人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Takao Watanabe

    IPC分类号： G06F12/12 ,  G06F13/00

    CPC分类号： G06F12/0607 ,  G06F12/0882

    摘要： In an information processing apparatus involving a cache accessed by INDEX and TAG addresses, accesses to the main memory include many accesses attributable to the local character of referencing and write-back accesses attributable to the replacement of cache contents. Accordingly, high speed accessing requires efficient assignment of the two kinds of accesses to banks of the DRAM. In assigning request addresses from the CPU to different banks of the DRAM, bank addresses of the DRAM and generated by operation of the INDEX field and the TAG field so that local accesses whose INDEX varies and accesses at the time of writing back of which INDEX remains the same but TAG differs can be assigned to different banks. High speed accessing is made possible because accesses to the main memory can be assigned to separate banks. Furthermore, as reading and writing at the time of writing back can be assigned to a separate bank, pseudo dual-port accessing is made possible with only one port, resulting in higher speed write-back accessing.

    摘要翻译： 在涉及由INDEX和TAG地址访问的高速缓冲存储器的信息处理装置中，对主存储器的访问包括归因于替代缓存内容的引用和回写访问的本地字符的许多访问。 因此，高速存取需要对DRAM的存储体的两种访问进行有效的分配。 在将请求地址从CPU分配给DRAM的不同组时，DRAM的存储区地址并通过INDEX字段和TAG字段的操作生成，以便INDEX在写入INDEX时保留的本地访问变化并访问 相同但TAG不同可以分配给不同的银行。 高速访问是可能的，因为可以将主存储器的访问分配给单独的存储区。 此外，由于在回写时的读写可以分配给单独的存储区，因此只能使用一个端口进行伪双端口访问，从而实现更高速的写回访问。

    Semiconductor integrated circuit device
    87.
    发明申请
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US20060291110A1

    公开(公告)日：2006-12-28

    申请号：US11447168

    申请日：2006-06-06

    申请人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Yoshihiko Yasu ,  Kenji Hirose ,  Takahiro Irita

    发明人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Yoshihiko Yasu ,  Kenji Hirose ,  Takahiro Irita

    IPC分类号： H02H7/00

    CPC分类号： H01L27/11898 ,  G06F17/5068 ,  G06F17/5072 ,  G11C11/419 ,  H01L23/48 ,  H01L23/50 ,  H01L23/528 ,  H01L27/00 ,  H01L27/02 ,  H01L27/0203 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/7835 ,  H01L2027/11881 ,  H01L2924/0002 ,  H03K3/0315 ,  H03K3/0375 ,  H03K17/16 ,  H01L2924/00

    摘要： A semiconductor integrated circuit device is provided, the circuit being capable of arranging a control signal system, avoiding a danger of failure to check an indefinite signal propagation prevention circuit or the like, further facilitating a check oriented to mounting on an automated tool, and facilitating power shutdown control inside of a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains Area A to Area I. A rule is provided, the rule defining that, in the case where a circuit having a high priority is turned ON, a power domain having its lower priority cannot be turned OFF, thereby facilitating a designing method. In addition, areas capable of applying still another power supply are provided in the independent power areas Area A to Area I. In that area, a relay buffer (repeater) and a clock buffer or an information retaining latch for saving information are integrated. A layout may be provided in a direction vertical to a direction in which cells are arranged in a row direction for the purpose of dispersing a current of a light supply line.

    摘要翻译： 提供了一种半导体集成电路器件，该电路能够布置控制信号系统，避免不能检查不确定的信号传播防止电路等的危险，进一步便于针对安装在自动化工具上的检查，并且促进 功率关断控制芯片内部。 在半导体集成电路装置中，功率关闭优先级由独立的电源区域A至区域I提供。规定了在具有高优先级的电路被接通的情况下，规定了具有 其较低优先级不能关闭，从而有助于设计方法。 此外，在独立电源区域A至区域I中提供能够应用另一电源的区域。在该区域中，集成了用于保存信息的中继缓冲器（中继器）和时钟缓冲器或信息保持锁存器。 为了分散供电线的电流，布置可以沿垂直于单元布置在行方向上的方向设置。

    Semiconductor device with level converter having signal-level shifting block and signal-level determination block
    88.
    发明申请
    Semiconductor device with level converter having signal-level shifting block and signal-level determination block 有权

    公开(公告)号：US20060197579A1

    公开(公告)日：2006-09-07

    申请号：US11410956

    申请日：2006-04-26

    申请人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Takeshi Sakata ,  Takao Watanabe

    发明人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Takeshi Sakata ,  Takao Watanabe

    IPC分类号： H03L5/00

    CPC分类号： H03K19/0016 ,  H03K19/018521

    摘要： A semiconductor device including a level converter (LSC) is disclosed. The level converter comprises a voltage-up circuit (LSC1) that operates on low voltage of power supply (VDD) and steps up voltage enough to drive the level converter and a level converter circuit (LSC2) that operates on high voltage of power supply (VDDQ). The voltage-up circuit is capable of constantly generating 2×VDD so that the level converter can convert a low voltage of power supply (VDD) below 1 V to VDDQ. This voltage-up circuit can be configured only with MOSFET transistors produced by thin oxide film deposition, thus enabling high-speed operation. To facilitate designing a circuit for preventing a leakage current from occurring in the level converter during sleep mode of a low-voltage-driven circuit (CB1), the level converter circuit (LSC2) includes a leak protection circuit (LPC) that exerts autonomous control for leak prevention, dispensing with external control signals.

    Semiconductor integrated circuit device
    90.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US07023058B2

    公开(公告)日：2006-04-04

    申请号：US10921854

    申请日：2004-08-20

    申请人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Naohiko Irie

    发明人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Naohiko Irie

    IPC分类号： H01L29/76 ,  H01L23/48

    CPC分类号： G01R31/318572 ,  G11C5/063 ,  G11C11/417 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/11807 ,  H01L2924/0002 ,  H03K3/356008 ,  H03K3/35625 ,  H03K19/0016 ,  H01L2924/00

    摘要： In a low power consumption mode in which prior data is retained upon power shutdown, the return speed thereof is increased. While use of an existent data retaining flip-flop may be considered, this is not preferred since it increases area overhead such as enlargement of the size of a cell. A power line for data retention for power shutdown is formed with wirings finer than a usual main power line. Preferably, power lines for a data retention circuit are considered as signal lines and wired by automatic placing and mounting. For this purpose, terminals for the power line for data retention are previously designed by providing the terminals therefor for the cell in the same manner as in the existent signal lines. Additional layout for power lines is no longer necessary for the cell, which enables a decrease in the area and design by an existent placing and routing tool.

    摘要翻译： 在功率关闭时保留先前数据的低功耗模式下，其返回速度增加。 虽然可以考虑使用现有的数据保持触发器，但是这不是优选的，因为它增加了诸如扩大单元大小的面积开销。 用于电源关闭的数据保持的电源线由比通常的主电源线更细的布线形成。 优选地，用于数据保持电路的电力线被认为是信号线，并通过自动放置和安装进行布线。 为此，先前通过以与现有信号线相同的方式为小区提供终端来设计用于数据保持的电力线的终端。 电池线的附加布局不再需要，这使得现有的放置和布线工具能够减少面积和设计。