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    Liquid ejection head
    82.
    发明申请
    Liquid ejection head 失效
    液体喷头

    公开(公告)号：US20050073556A1

    公开(公告)日：2005-04-07

    申请号：US10620421

    申请日：2003-07-17

    申请人： Toshiaki Sasaki ,  Keiichi Murai ,  Yasuyuki Tamura ,  Sadayuki Sugama ,  Akira Asai ,  Tsutomu Kawai ,  Masayoshi Tachihara

    发明人： Toshiaki Sasaki ,  Keiichi Murai ,  Yasuyuki Tamura ,  Sadayuki Sugama ,  Akira Asai ,  Tsutomu Kawai ,  Masayoshi Tachihara

    IPC分类号： A61M15/00 ,  A61M15/02 ,  B05B1/24 ,  B41J2/14 ,  B41J2/05

    CPC分类号： B41J2/1404 ,  A61M15/0065 ,  A61M15/02 ,  A61M15/025 ,  B41J2/14016 ,  B41J2/1412 ,  B41J2/1433 ,  B41J2002/14387 ,  B41J2002/14475

    摘要： A liquid ejection head includes a liquid path; an ejection outlet forming member which constitutes a part of a wall of the liquid and which forms an ejection outlet for ejecting a droplet of liquid; a heat generating element, provided at a position opposing to the ejection outlet of the wall of the liquid flow path, for generating a bubble in the liquid by application of heat to the liquid; a restrictor portion, provided at a recessed portion of the ejection outlet, wherein the recessed portion is recessed from a plane in which the ejection outlet is formed, wherein the liquid forms a meniscus and is retained in the ejection outlet such that the restrictor portion is within the liquid, wherein an area So of an opening of the restrictor portion and a surface Sh of the heat generating element satisfy So≦Sh. According to this invention, a central portion of the meniscus opposed to the fine opening at the ejection outlet bulges, and the liquid is ejected in this state. Namely, very small amount of the liquid can be ejected, since not all of the liquid in the recess portion in the ejection outlet is ejected.

    摘要翻译： 液体喷射头包括液体通道; 喷射出口形成构件，其构成液体壁的一部分并且形成用于喷射液滴的喷射出口; 发热元件，设置在与液体流路的壁的喷射出口相对的位置处，用于通过向液体施加热量而在液体中产生气泡; 设置在所述喷射出口的凹陷部分处的所述限制器部分，其中所述凹部从形成所述喷射出口的平面凹陷，其中所述液体形成弯液面并保持在所述喷射出口中，使得所述限制器部分 在液体内，限制器部分的开口的面积So和发热元件的表面Sh满足So <= Sh。 根据本发明，与喷射出口处的微细开口相对的弯月面的中心部分凸出，并且在该状态下喷射液体。 也就是说，由于喷出口的凹部内的液体并不全部喷出，因此能够喷射非常少量的液体。

    Semiconductor device and method for fabricating the same
    83.
    发明授权
    Semiconductor device and method for fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号：US06713790B2

    公开(公告)日：2004-03-30

    申请号：US10212799

    申请日：2002-08-07

    申请人： Akira Asai ,  Teruhito Oonishi ,  Takeshi Takagi ,  Tohru Saitoh ,  Yoshihiro Hara ,  Koichiro Yuki ,  Katsuya Nozawa ,  Yoshihiko Kanzawa ,  Koji Katayama ,  Yo Ichikawa

    发明人： Akira Asai ,  Teruhito Oonishi ,  Takeshi Takagi ,  Tohru Saitoh ,  Yoshihiro Hara ,  Koichiro Yuki ,  Katsuya Nozawa ,  Yoshihiko Kanzawa ,  Koji Katayama ,  Yo Ichikawa

    IPC分类号： H01L31072

    CPC分类号： H01L29/66242 ,  H01L21/763 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/7378

    摘要： In the method for fabricating a semiconductor device of the present invention, a collector layer of a first conductivity type is formed in a region of a semiconductor substrate sandwiched by device isolation. A collector opening is formed through a first insulating layer deposited on the semiconductor substrate so that the range of the collector opening covers the collector layer and part of the device isolation. A semiconductor layer of a second conductivity type as an external base is formed on a portion of the semiconductor substrate located inside the collector opening, while junction leak prevention layers of the same conductivity type as the external base are formed in the semiconductor substrate. Thus, the active region is narrower than the collector opening reducing the transistor area, while minimizing junction leak.

    摘要翻译： 在本发明的半导体装置的制造方法中，在被器件分离夹持的半导体基板的区域中形成有第一导电型的集电极层。 通过沉积在半导体衬底上的第一绝缘层形成集电极开口，使得集电极开口的范围覆盖集电极层和器件隔离的一部分。 在位于集电体开口内部的半导体基板的一部分上形成作为外部基底的第二导电类型的半导体层，同时在半导体衬底中形成与外部基底相同的导电类型的防漏层。 因此，有源区域比集电极开口窄，减小晶体管面积，同时最小化结漏电。

    Method for driving a non-volatile semiconductor memory
    87.
    发明授权
    Method for driving a non-volatile semiconductor memory 失效
    用于驱动非易失性半导体存储器的方法

    公开(公告)号：US5715196A

    公开(公告)日：1998-02-03

    申请号：US684178

    申请日：1996-07-19

    申请人： Yoshinori Odake ,  Akira Asai ,  Yasushi Okuda ,  Toshiki Mori ,  Ichirou Nakao

    发明人： Yoshinori Odake ,  Akira Asai ,  Yasushi Okuda ,  Toshiki Mori ,  Ichirou Nakao

    IPC分类号： G11C16/04 ,  G11C16/26 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

    CPC分类号： H01L27/11521 ,  G11C16/0416 ,  G11C16/26 ,  H01L27/115 ,  H01L29/66825 ,  H01L29/7883

    摘要： An array of non-volatile memory cells arranged in rows and columns is provided. Each memory cell is composed of a transistor made up of a gate, a source, and drain and a capacitance section. Each memory cell is connected to a row decoder through a wordline, to a column decoder through a bitline, and to a source decoder through a sourceline. Arranged in a path extending from a bitline to a sourceline through a transistor is an anisotropic resistance section, e.g., a diode, exhibiting different voltage-current characteristics for different levels of voltages applied thereacross. Because of such arrangement, leakage current occurring to a deselected memory cell in a reading operation can be reduced or can be eliminated. Read errors due to leakage current can be avoided and the power consumption can be reduced.

    摘要翻译： 提供了排列成行和列的非易失性存储单元阵列。 每个存储单元由由栅极，源极和漏极以及电容部分构成的晶体管构成。 每个存储单元通过字线连接到行解码器，通过位线连接到列解码器，并通过源线连接到源解码器。 在从位线延伸到源极线通过晶体管的路径中布置的是各向异性电阻部分，例如二极管，对于施加在其上的不同电压电平，具有不同的电压 - 电流特性。 由于这样的布置，可以减少或可以消除在读取操作中对取消选择的存储单元发生的泄漏电流。 可以避免由于泄漏电流而导致的读取错误，并且可以降低功耗。

    Non-volatile semiconductor memory having an array of non-volatile memory cells and method for driving the same
    88.
    发明授权
    Non-volatile semiconductor memory having an array of non-volatile memory cells and method for driving the same 失效
    具有非易失性存储单元阵列的非易失性半导体存储器及其驱动方法

    公开(公告)号：US5627779A

    公开(公告)日：1997-05-06

    申请号：US505638

    申请日：1995-07-21

    申请人： Yoshinori Odake ,  Akira Asai ,  Yasushi Okuda ,  Toshiki Mori ,  Ichirou Nakao

    发明人： Yoshinori Odake ,  Akira Asai ,  Yasushi Okuda ,  Toshiki Mori ,  Ichirou Nakao

    IPC分类号： G11C16/04 ,  G11C16/26 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  G11C16/02

    CPC分类号： H01L27/11521 ,  G11C16/0416 ,  G11C16/26 ,  H01L27/115 ,  H01L29/66825 ,  H01L29/7883

    摘要： An array of non-volatile memory cells arranged in rows and columns is provided. Each memory cell is composed of a transistor made up of a gate, a source, and drain and a capacitance section. Each memory cell is connected to a row decoder through a wordline, to a column decoder through a bitline, and to a source decoder through a sourceline. Arranged in a path extending from a bitline to a sourceline through a transistor is an anisotropic resistance section, e.g., a diode, exhibiting different voltage-current characteristics for different levels of voltages applied thereacross. Because of such arrangement, leakage current occurring to a deselected memory cell in a reading operation can be reduced or can be eliminated. Read errors due to leakage current can be avoided and the power consumption can be reduced.

    摘要翻译： 提供了排列成行和列的非易失性存储单元阵列。 每个存储单元由由栅极，源极和漏极以及电容部分构成的晶体管构成。 每个存储单元通过字线连接到行解码器，通过位线连接到列解码器，并通过源线连接到源解码器。 在从位线延伸到源极线通过晶体管的路径中布置的是各向异性电阻部分，例如二极管，对于施加在其上的不同电压电平，具有不同的电压 - 电流特性。 由于这样的布置，可以减少或可以消除在读取操作中对取消选择的存储单元发生的泄漏电流。 可以避免由于泄漏电流而导致的读取错误，并且可以降低功耗。

    Semiconductor device and method of manufacturing the same
    89.
    发明授权
    Semiconductor device and method of manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号：US5459341A

    公开(公告)日：1995-10-17

    申请号：US195165

    申请日：1994-02-14

    申请人： Tomofumi Shono ,  Akira Asai ,  Masanori Fukumoto

    发明人： Tomofumi Shono ,  Akira Asai ,  Masanori Fukumoto

    IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L29/68

    CPC分类号： H01L27/10852 ,  H01L27/10808

    摘要： A surface region of a P-type semiconductor substrate is defined by an isolation into plural active regions at which a semiconductor element is to be formed. A first diffusion region such as a drain region, a second diffusion region such as a source region, and a wiring member such as a word line are arranged at each active region. The surface of the word line is covered with a first insulating layer. A second insulating layer is provided, in which a region including in common each overhead region on at least two second diffusion regions is removed, leaving an overhead region on the first diffusion region. Provided above the second diffusion region is a conductive member such as a capacity storage electrode, a bit line. A contact member which connects the conductive member and the second diffusion region is formed at a region where the second insulating layer is removed. With the second insulating layer of such configuration, an increase in connection resistance and a connection defect of the capacity storage electrode contact or the bit line contact are prevented.

    摘要翻译： P型半导体衬底的表面区域通过隔离形成半导体元件的多个有源区域来限定。 在每个有源区域上布置有诸如漏极区域的第一扩散区域，诸如源极区域的第二扩散区域和诸如字线的布线构件。 字线的表面被第一绝缘层覆盖。 提供了第二绝缘层，其中除去在至少两个第二扩散区域上共同的每个塔顶区域的区域，在第一扩散区域上留下顶部区域。 设置在第二扩散区域之上的是诸如容量存储电极，位线的导电构件。 连接导电部件和第二扩散区域的接触部件形成在除去第二绝缘层的区域。 通过这种结构的第二绝缘层，防止了电容存储电极接触或位线接触的连接电阻的增加和连接缺陷。