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    SONOS STACK WITH SPLIT NITRIDE MEMORY LAYER
    82.
    发明申请
    SONOS STACK WITH SPLIT NITRIDE MEMORY LAYER 有权
    SONOS堆叠分离硝酸盐存储层

    公开(公告)号：US20130175600A1

    公开(公告)日：2013-07-11

    申请号：US13431069

    申请日：2012-03-27

    Applicant: Fredrick Jenne ,  Krishnaswamy Ramkumar

    Inventor： Fredrick Jenne ,  Krishnaswamy Ramkumar

    IPC: H01L29/792 ,  H01L21/336

    CPC classification number: H01L29/792 ,  B82Y10/00 ,  H01L21/28282 ,  H01L29/513 ,  H01L29/785 ,  H01L29/7926

    Abstract: Embodiments of a non-planar memory device including a split charge-trapping region and methods of forming the same are described. Generally, the device comprises: a channel formed from a thin film of semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide overlying the channel; a split charge-trapping region overlying the tunnel oxide, the split charge-trapping region including a bottom charge-trapping layer comprising a nitride closer to the tunnel oxide, and a top charge-trapping layer, wherein the bottom charge-trapping layer is separated from the top charge-trapping layer by a thin anti-tunneling layer comprising an oxide. Other embodiments are also disclosed.

    Abstract translation: 描述了包括分离电荷捕获区域的非平面存储器件及其形成方法的实施例。 通常，该器件包括：由覆盖存储器件的源极和漏极的衬底上的表面的半导体材料薄膜形成的沟道; 覆盖通道的隧道氧化物; 分离电荷捕获区域，覆盖隧道氧化物，分离电荷捕获区域包括底部电荷捕获层，其包含更接近隧道氧化物的氮化物，以及顶部电荷捕获层，其中底部电荷捕获层被分离 从顶部的电荷捕获层通过包含氧化物的薄的抗隧道层。 还公开了其他实施例。

    INLINE METHOD TO MONITOR ONO STACK QUALITY
    83.
    发明申请
    INLINE METHOD TO MONITOR ONO STACK QUALITY 有权
    用于监控堆栈质量的在线方法

    公开(公告)号：US20130175599A1

    公开(公告)日：2013-07-11

    申请号：US13430631

    申请日：2012-03-26

    Applicant: Yu Yang ,  Krishnaswamy Ramkumar

    Inventor： Yu Yang ,  Krishnaswamy Ramkumar

    IPC: H01L29/792 ,  H01L21/66

    CPC classification number: H01L29/792 ,  H01L22/14 ,  H01L29/66833

    Abstract: Embodiments of structures and methods for determining operating characteristics of a non-volatile memory transistor comprising a charge-storage-layer and a tunneling-layer are described. In one embodiment, the method comprises: forming on a substrate a structure including a nitrided tunneling-layer and a charge-storage-layer overlying the tunneling-layer comprising a first charge-storage layer adjacent to the tunneling-layer, and a second charge-storage layer overlying the first charge-storage layer, wherein the first charge-storage layer is separated from the second charge-storage layer by a anti-tunneling layer comprising an oxide; depositing a positive charge on the charge-storage-layer and determining a first voltage to establish a first leakage current through the charge-storage-layer and the tunneling-layer; depositing a negative charge on the charge-storage-layer and determining a second voltage to establish a second leakage current through the charge-storage-layer and the tunneling-layer; and determining a differential voltage by calculating a difference between the first and second voltages.

    Abstract translation: 描述了用于确定包括电荷存储层和隧穿层的非易失性存储晶体管的操作特性的结构和方法的实施例。 在一个实施例中，该方法包括：在衬底上形成包括氮化隧道层和覆盖隧道层的电荷存储层的结构，该隧穿层包括与隧道层相邻的第一电荷存储层和第二电荷 覆盖在第一电荷存储层上的第一电荷存储层，其中第一电荷存储层通过包含氧化物的反隧道层与第二电荷存储层分离; 在电荷存储层上沉积正电荷并确定第一电压以建立通过电荷存储层和隧道层的第一泄漏电流; 在电荷存储层上沉积负电荷并确定第二电压以建立通过电荷存储层和隧穿层的第二泄漏电流; 以及通过计算所述第一和第二电压之间的差来确定差分电压。

    Semiconductor topography including a thin oxide-nitride stack and method for making the same
    87.
    发明授权
    Semiconductor topography including a thin oxide-nitride stack and method for making the same 有权
    包括薄氧化物氮化物堆叠的半导体形貌及其制造方法

    公开(公告)号：US07365403B1

    公开(公告)日：2008-04-29

    申请号：US10074884

    申请日：2002-02-13

    Applicant: Krishnaswamy Ramkumar

    Inventor： Krishnaswamy Ramkumar

    IPC: H01L27/108

    CPC classification number: H01L21/28282 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02233 ,  H01L21/02271 ,  H01L21/28202 ,  H01L21/28273 ,  H01L21/3143 ,  H01L29/513 ,  H01L29/518

    Abstract: A semiconductor topography is provided which includes a silicon dioxide layer with a thickness equal to or less than approximately 10 angstroms and a silicon nitride layer arranged upon the silicon dioxide layer. In addition, a method is provided which includes growing an oxide film upon a semiconductor topography in the presence of an ozonated substance and depositing a silicon nitride film upon the oxide film. In some embodiments, the method may include growing the oxide film in a first chamber at a first temperature and transferring the semiconductor topography from the first chamber to a second chamber while the semiconductor topography is exposed to a substantially similar temperature as the first temperature. In either embodiment, the method may be used to form a semiconductor device including an oxide-nitride gate dielectric having an electrical equivalent oxide gate dielectric thickness of less than approximately 20 angstroms.

    Abstract translation: 提供半导体形貌，其包括厚度等于或小于约10埃的二氧化硅层和布置在二氧化硅层上的氮化硅层。 此外，提供了一种方法，其包括在存在臭氧化物质的情况下在半导体形貌上生长氧化膜并在氧化物膜上沉积氮化硅膜。 在一些实施例中，该方法可以包括在第一温度下在第一室中生长氧化膜并将半导体形貌从第一室转移到第二室，同时将半导体形貌暴露于与第一温度基本相似的温度。 在任一实施例中，该方法可以用于形成包括具有小于约20埃的电等效氧化物栅极介电厚度的氧化物 - 氮化物栅极电介质的半导体器件。

    Method of manufacturing an oxide-nitride-oxide (ONO) dielectric for SONOS-type devices
    88.
    发明授权
    Method of manufacturing an oxide-nitride-oxide (ONO) dielectric for SONOS-type devices 有权
    用于SONOS型器件的氧化物 - 氮化物（ONO）电介质的制造方法

    公开(公告)号：US06969689B1

    公开(公告)日：2005-11-29

    申请号：US10184715

    申请日：2002-06-28

    Applicant: Krishnaswamy Ramkumar ,  Manuj Rathor ,  Biju Parameshwaran ,  Loren Lancaster

    Inventor： Krishnaswamy Ramkumar ,  Manuj Rathor ,  Biju Parameshwaran ,  Loren Lancaster

    IPC: H01L21/28 ,  H01L21/31 ,  H01L21/314 ,  H01L21/469 ,  H01L21/8246 ,  H01L27/115

    CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L21/3144 ,  H01L27/115

    Abstract: A method of forming oxide-nitride-oxide (ONO) dielectric of a SONOS-type nonvolatile storage device is disclosed. According to a first embodiment, a method may include the steps of forming a tunneling dielectric (step 102), forming a charge storing dielectric (step 104), and forming a top insulating layer (step 106) all in the same wafer processing tool. According to various aspects of the embodiments, all layers of an ONO dielectric of a SONOS-type device may be formed in the same general temperature range. Further, a tunneling dielectric may include a tunnel oxide formed with a long, low pressure oxidation, and a top insulating layer may include silicon dioxide formed with a preheated source gas.

    Abstract translation: 公开了一种形成SONOS型非易失性存储装置的氧化物 - 氧化物 - 氧化物（ONO）电介质的方法。 根据第一实施例，一种方法可以包括以下步骤：形成隧道电介质（步骤102），形成电荷存储电介质（步骤104），以及在相同的晶片处理工具中形成顶部绝缘层（步骤106）。 根据实施例的各个方面，SONOS型器件的ONO电介质的所有层可以形成在相同的一般温度范围内。 此外，隧道电介质可以包括形成有长的低压氧化的隧道氧化物，并且顶部绝缘层可以包括用预热的源气体形成的二氧化硅。

    Self-aligned contact structure with raised source and drain
    89.
    发明授权
    Self-aligned contact structure with raised source and drain 有权
    具有升高的源极和漏极的自对准接触结构

    公开(公告)号：US06869850B1

    公开(公告)日：2005-03-22

    申请号：US10326525

    申请日：2002-12-20

    Applicant: Alain Blosse ,  Krishnaswamy Ramkumar

    Inventor： Alain Blosse ,  Krishnaswamy Ramkumar

    IPC: H01L21/60 ,  H01L29/417 ,  H01L21/336

    CPC classification number: H01L21/76897 ,  H01L29/41775 ,  H01L29/41783

    Abstract: In one embodiment, a transistor comprises raised structures over a source region and a drain region. The raised source structures may comprise selectively deposited metal, such as selective tungsten. A self-aligned contact structure formed through a dielectric layer may provide an electrical connection between an overlying structure (e.g., an interconnect line) and the source or drain region. The transistor may further comprise a gate stack having a capping layer over a metal.

    Abstract translation: 在一个实施例中，晶体管包括在源极区域和漏极区域上的凸起结构。 升高的源结构可以包括选择性沉积的金属，例如选择性钨。 通过电介质层形成的自对准接触结构可以在上覆结构（例如，互连线）和源极或漏极区之间提供电连接。 晶体管还可以包括在金属上具有覆盖层的栅极堆叠。

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