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    Nitride spacer formation
    2.
    发明授权
    Nitride spacer formation 有权
    氮化物间隔物形成

    公开(公告)号：US06803321B1

    公开(公告)日：2004-10-12

    申请号：US10313049

    申请日：2002-12-06

    Applicant: Alain Blosse ,  Krishnaswamy Ramkumar ,  Sundar Narayanan

    Inventor： Alain Blosse ,  Krishnaswamy Ramkumar ,  Sundar Narayanan

    IPC: H01I21302

    CPC classification number: H01L21/76897 ,  H01L21/28247 ,  H01L21/31116 ,  H01L21/3185

    Abstract: A method of forming a semiconductor structure comprises forming a nitride layer on a stack, and etching the nitride layer to form spacers in contact with sides of the stack. The stack is on a semiconductor substrate, the stack comprises (i) a gate layer, comprising silicon, (ii) a metallic layer, on the gate layer, and (iii) an etch-stop layer, on the metallic layer. The forming is by CVD with a gas comprising SixL2x, L is an amino group, and X is 1 or 2.

    Abstract translation: 形成半导体结构的方法包括在叠层上形成氮化物层，并蚀刻氮化物层以形成与堆叠的侧面接触的间隔物。 叠层在半导体衬底上，堆叠包括（i）栅极层，包括硅，（ii）栅极层上的金属层，和（iii）金属层上的蚀刻停止层。 通过CVD形成气体，其中包含SixL2x的气体，L是氨基，X是1或2。

    Formation of a shallow trench isolation structure in integrated circuits
    3.
    发明授权
    Formation of a shallow trench isolation structure in integrated circuits 有权
    在集成电路中形成浅沟槽隔离结构

    公开(公告)号：US06773975B1

    公开(公告)日：2004-08-10

    申请号：US10326707

    申请日：2002-12-20

    Applicant: Krishnaswamy Ramkumar ,  Sundar Narayanan ,  Shahin Sharifzadeh

    Inventor： Krishnaswamy Ramkumar ,  Sundar Narayanan ,  Shahin Sharifzadeh

    IPC: H01L218238

    CPC classification number: H01L21/823481 ,  H01L21/76229

    Abstract: In one embodiment, a transistor is fabricated by forming gate materials, such as a gate oxide layer and a gate polysilicon layer, prior to forming a shallow trench isolation (STI) structure. Forming the gate materials early in the process minimizes exposure of the STI structure to processing steps that may expose its corners. Also, to minimize cross-diffusion of dopants and to help lower gate resistance, a metal stack comprising a barrier layer and a metal layer may be employed as a conductive line between gates. In one embodiment, the metal stack comprises a barrier layer of tungsten-nitride and a metal layer of tungsten.

    Abstract translation: 在一个实施例中，在形成浅沟槽隔离（STI）结构之前，通过形成栅极材料，例如栅极氧化物层和栅极多晶硅层来制造晶体管。 在此过程早期形成栅极材料可最大限度地减少STI结构暴露其角落的处理步骤。 此外，为了最小化掺杂剂的交叉扩散并有助于降低栅极电阻，可以使用包括阻挡层和金属层的金属堆叠作为栅极之间的导电线。 在一个实施例中，金属堆叠包括氮化钨的阻挡层和钨的金属层。

    Method and structure for determining a concentration profile of an impurity within a semiconductor layer
    5.
    发明授权
    Method and structure for determining a concentration profile of an impurity within a semiconductor layer 有权
    用于确定半导体层内的杂质的浓度分布的方法和结构

    公开(公告)号：US06905893B1

    公开(公告)日：2005-06-14

    申请号：US10289020

    申请日：2002-11-05

    Applicant: Sundar Narayanan ,  Krishnaswamy Ramkumar

    Inventor： Sundar Narayanan ,  Krishnaswamy Ramkumar

    IPC: G01N1/32 ,  G01N19/06 ,  H01L21/66 ,  H01L23/544

    CPC classification number: H01L22/20 ,  G01N1/32 ,  G01N19/06 ,  H01L22/34

    Abstract: A method is provided for determining a concentration profile of an impurity within a layer of a semiconductor topography. The method may include exposing the layer and an underlying layer to oxidizing conditions. In addition, the method may include comparing thickness measurements of total dielectric above the underlying layer taken before and after exposing the topography to oxidizing conditions . In some cases, the comparison may include plotting pre-oxidation thickness measurements versus post-oxidation measurements. In other embodiments, the comparison may include determining differences between the pre-oxidation and post-oxidation thickness measurements and correlating the differences to concentrations of the impurity. In some cases, such a correlation may include subtracting a concentration of the impurity at a first location along the semiconductor topography from a concentration of the impurity at a second location along the semiconductor topography.

    Abstract translation: 提供了一种用于确定半导体形貌层内的杂质的浓度分布的方法。 该方法可以包括将层和下层暴露于氧化条件。 此外，该方法可以包括将暴露于地形之前和之后的所述下层的总电介质的厚度测量值与氧化条件进行比较。 在某些情况下，比较可能包括绘制预氧化厚度测量值与氧化后测量值。 在其他实施例中，比较可以包括确定预氧化和后氧化厚度测量之间的差异并将差异与杂质的浓度相关联。 在一些情况下，这种相关可以包括沿着半导体形貌从第二位置处的杂质浓度减去沿着半导体形貌的第一位置处的杂质的浓度。

    Selective oxidation of gate stack
    7.
    发明授权
    Selective oxidation of gate stack 有权
    选择性氧化栅极叠层

    公开(公告)号：US07189652B1

    公开(公告)日：2007-03-13

    申请号：US10313048

    申请日：2002-12-06

    Applicant: Alain Blosse ,  Sundar Narayanan ,  Krishnaswamy Ramkumar

    Inventor： Alain Blosse ,  Sundar Narayanan ,  Krishnaswamy Ramkumar

    IPC: H01L21/302

    CPC classification number: H01L21/28247 ,  H01L21/28061

    Abstract: A method of forming a semiconductor structure comprises oxidizing a stack, to form sidewall oxide in contact with sides of the stack. The stack is on a semiconductor substrate, the stack includes a gate layer, comprising silicon; a metallic layer, on the gate layer; and an etch-stop layer, on the metallic layer. The sidewall oxide in contact with the metallic layer is thinner than the sidewall oxide in contact with the gate layer.

    Abstract translation: 形成半导体结构的方法包括氧化堆叠，以形成与堆叠的侧面接触的侧壁氧化物。 堆叠在半导体衬底上，堆叠包括包含硅的栅极层; 栅极层上的金属层; 和金属层上的蚀刻停止层。 与金属层接触的侧壁氧化物比与栅极层接触的侧壁氧化物薄。

    Method of forming nitrided oxide in a hot wall single wafer furnace
    8.
    发明授权
    Method of forming nitrided oxide in a hot wall single wafer furnace 有权
    在热壁单晶圆炉中形成氮化氧化物的方法

    公开(公告)号：US07094707B1

    公开(公告)日：2006-08-22

    申请号：US10142963

    申请日：2002-05-13

    Applicant: Krishnaswamy Ramkumar ,  Sundar Narayanan

    Inventor： Krishnaswamy Ramkumar ,  Sundar Narayanan

    IPC: H01L23/58

    CPC classification number: H01L21/28202 ,  H01L21/28035 ,  H01L29/518

    Abstract: A method of nitriding a gate oxide layer by annealing a preformed oxide layer with nitric oxide (NO) gas in a hot wall, single wafer furnace is provided. The nitridation process can be carried out rapidly (i.e., at nitridation times of 30 seconds to 2 minutes) while providing acceptable levels of nitridation (i.e., up to 6 at. %) and desirable nitrogen/depth profiles. The nitrided gate oxide layer can optionally be reoxidized in a second oxidation step after the nitridation step. A gate electrode layer (e.g., boron doped polysilicon) can then be deposited on top of the nitrided gate oxide layer or on top of the reoxidized and nitrided gate oxide layer.

    Abstract translation: 提供了一种通过在热壁中的一氧化氮（NO）气体退火预形成的氧化物层来对栅极氧化物层进行氮化的方法。 氮化处理可以快速进行（即，在30秒至2分钟的氮化时间），同时提供可接受的氮化水平（即高达6原子％）和所需的氮/深度分布。 氮化栅氧化层可以在氮化步骤后的第二氧化步骤中任选地再氧化。 然后可以在氮化栅极氧化物层的顶部上或在再氧化和氮化的栅极氧化物层的顶部上沉积栅极电极层（例如，硼掺杂的多晶硅）。

    Method for and structure formed from fabricating a relatively deep isolation structure
    10.
    发明授权
    Method for and structure formed from fabricating a relatively deep isolation structure 有权
    通过制造相对较深的隔离结构形成的方法和结构

    公开(公告)号：US06794269B1

    公开(公告)日：2004-09-21

    申请号：US10324989

    申请日：2002-12-20

    Applicant: Prabhuram Gopalan ,  Biju Parameshwaran ,  Krishnaswamy Ramkumar ,  Hanna Bamnolker ,  Sundar Narayanan

    Inventor： Prabhuram Gopalan ,  Biju Parameshwaran ,  Krishnaswamy Ramkumar ,  Hanna Bamnolker ,  Sundar Narayanan

    IPC: H01L2176

    CPC classification number: H01L21/763 ,  H01L21/76202

    Abstract: A method is provided which includes forming a deep isolation structure within a semiconductor topography. In some cases, the method may include forming a first isolation structure within a semiconductor layer and etching an opening within the isolation structure to expose the semiconductor layer. In addition, the method may include etching the semiconductor layer to form a trench extending through the isolation structure and at least part of the semiconductor layer. In some cases, the method may include removing part of a first fill layer deposited within the trench such that an upper surface of the fill layer is below an upper portion of the trench. In such an embodiment, the vacant portion of the trench may be filled with a second fill layer. In yet other embodiments, the method may include planarizing the first fill layer within the trench and subsequently oxidizing an upper portion of the fill layer.

    Abstract translation: 提供了一种方法，其包括在半导体形貌内形成深度隔离结构。 在一些情况下，该方法可以包括在半导体层内形成第一隔离结构并蚀刻隔离结构内的开口以暴露半导体层。 此外，该方法可以包括蚀刻半导体层以形成延伸穿过隔离结构和半导体层的至少一部分的沟槽。 在一些情况下，该方法可以包括去除沉积在沟槽内的第一填充层的部分，使得填充层的上表面在沟槽的上部下方。 在这样的实施例中，沟槽的空缺部分可以填充第二填充层。 在其他实施例中，该方法可以包括平坦化沟槽内的第一填充层，随后氧化填充层的上部。

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