公开(公告)号：US06900002B1

公开(公告)日：2005-05-31

申请号：US10299427

申请日：2002-11-19

申请人： Marina V. Plat ,  Marilyn I. Wright ,  Lu You ,  Scott A. Bell

发明人： Marina V. Plat ,  Marilyn I. Wright ,  Lu You ,  Scott A. Bell

IPC分类号： G03F7/00 ,  G03F7/09 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/3213

CPC分类号： H01L21/32139 ,  G03F7/091 ,  H01L21/0276 ,  H01L21/31058

摘要： An amorphous carbon layer of an antireflective bi-layer hardmask is processed to increase its density prior to patterning of an underlying polysilicon layer using the bi-layer hardmask. The increased density of the layer increases its resistance to polysilicon etch chemistry, thus reducing the likelihood of patterning inaccuracies resulting from amorphous carbon depletion during polysilicon etch, and enabling the patterning of thicker polysilicon layers than can be reliably patterned without densification. The increased density also reduces stresses, thus reducing the likelihood of delamination. Densification may be performed by UV or e-beam irradiation after formation of an overlying protective layer. Densification may also be performed by annealing the amorphous carbon layer in situ prior to formation of the overlying protective layer. In the latter case, annealing reduces the amount of outgassing that occurs during formation of the protective layer, thus reducing the formation of pin holes.

摘要翻译： 在使用双层硬掩模对下面的多晶硅层进行图案化之前，处理抗反射双层硬掩模的无定形碳层以增加其密度。 层的增加的密度增加了其对多晶硅蚀刻化学性质的抵抗力，从而降低了在多晶硅蚀刻期间由无定形碳耗尽导致的不准确图案的可能性，并且使得能够在不致密化的情况下可靠地图案化更厚的多晶硅层的图案化。 增加的密度也降低了应力，从而降低了分层的可能性。 在形成上覆保护层之后，可以通过UV或电子束照射进行致密化。 还可以通过在形成上覆保护层之前将非晶碳层原位退火来进行致密化。 在后一种情况下，退火减少了在形成保护层期间发生的除气量，从而减少了针孔的形成。

公开(公告)号：US06794298B2

公开(公告)日：2004-09-21

申请号：US09498336

申请日：2000-02-04

申请人： Jeffrey A. Shields ,  Lu You ,  Mohammad R. Rakhshandehroo

发明人： Jeffrey A. Shields ,  Lu You ,  Mohammad R. Rakhshandehroo

IPC分类号： H01L2120

CPC分类号： H01L21/02063 ,  H01L21/31138 ,  H01L21/76802 ,  H01L21/76814

摘要： The degradation of deposited low dielectric constant interlayer dielectrics and gap fill layers, such as HSQ layers, during formation of contacts/vias is significantly reduced or prevented by employing a plasma containing CF4+H2O to remove the photoresist mask and cleaning the contact/via opening after anisotropic etching. The CF4+H2O plasma also enables rapid photoresist stripping at a rate of about 10 to about 20 KÅ/min. Embodiments include photoresist stripping and cleaning the contact/via opening with a CF4+H2O plasma to prevent reduction of the number of Si—H bonds of an as-deposited HSQ layer below about 70%.

摘要翻译： 通过使用含有CF 4 + H 2 O的等离子体去除光致抗蚀剂掩模并清洁接触/通孔，显着降低或防止沉积的低介电常数层间电介质和间隙填充层（例如HSQ层）在形成接触/通孔期间的劣化 各向异性蚀刻后。 CF4 + H2O等离子体还可以以约10至约20K埃/分钟的速率快速地进行光致抗蚀剂剥离。 实施方案包括光致抗蚀剂剥离和用CF 4 + H 2 O等离子体清洁接触/通孔开口，以防止沉积的HSQ层的Si-H键的数量降低到约70％以下。

公开(公告)号：US06773998B1

公开(公告)日：2004-08-10

申请号：US10445129

申请日：2003-05-20

申请人： Philip A. Fisher ,  Marina V. Plat ,  Chih-Yuh Yang ,  Christopher F. Lyons ,  Scott A. Bell ,  Douglas J. Bonser ,  Lu You ,  Srikanteswara Dakshina-Murthy

发明人： Philip A. Fisher ,  Marina V. Plat ,  Chih-Yuh Yang ,  Christopher F. Lyons ,  Scott A. Bell ,  Douglas J. Bonser ,  Lu You ,  Srikanteswara Dakshina-Murthy

IPC分类号： H01L21336

CPC分类号： H01L21/0276 ,  H01L21/0332 ,  H01L21/28123 ,  H01L21/31116 ,  H01L21/3146 ,  H01L21/32137 ,  H01L21/32139

摘要： A method for an integrated circuit includes the use of an amorphous carbon ARC mask. A layer of amorphous carbon material is deposited above a layer of conductive material, and a layer of anti-reflective coating (ARC) material is deposited over the layer of amorphous carbon material. The layer of amorphous carbon material and the layer of ARC material are etched to form a mask comprising an ARC material portion and an amorphous carbon portion. A feature may then be formed in the layer of conductive material by etching the layer of conductive material in accordance with the mask.

摘要翻译： 集成电路的方法包括使用无定形碳ARC掩模。 一层非晶碳材料沉积在导电材料层上方，并且一层抗反射涂层（ARC）材料沉积在无定形碳材料层上。 蚀刻无定形碳材料层和ARC材料层以形成包含ARC材料部分和无定形碳部分的掩模。 然后可以通过根据掩模蚀刻导电材料层而在导电材料层中形成特征。

公开(公告)号：US06724087B1

公开(公告)日：2004-04-20

申请号：US10331682

申请日：2002-12-30

申请人： Matthew S. Buynoski ,  Paul R. Besser ,  Sergey D. Lopatin ,  Lu You

发明人： Matthew S. Buynoski ,  Paul R. Besser ,  Sergey D. Lopatin ,  Lu You

IPC分类号： H01L2348

CPC分类号： H01L21/76877 ,  H01L21/76847 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating an integrated circuit can include forming a laminated conductive line. The laminated conductive line can be formed in a dielectric trench. The laminated conductive line can include alternating barrier layers and copper layers. An integrated circuit includes at least one interconnect layer, the interconnect layer including a number of conductive lines. Each of the conductive lines includes a first thin barrier layer, a first thin copper layer, a second thin barrier layer and a second thin copper layer. The layered or laminated structure can reduce unconstrained void formation.

摘要翻译： 集成电路的制造方法可以包括形成叠层导电线。 层叠导电线可以形成在电介质沟槽中。 层叠导电线可以包括交替的阻挡层和铜层。 集成电路包括至少一个互连层，所述互连层包括多个导电线。 每个导线包括第一薄势垒层，第一薄铜层，第二薄阻挡层和第二薄铜层。 分层或层压结构可以减少无约束的空隙形成。

公开(公告)号：US06713874B1

公开(公告)日：2004-03-30

申请号：US09817050

申请日：2001-03-27

申请人： Dawn M. Hopper ,  Lu You ,  Minh Van Ngo

发明人： Dawn M. Hopper ,  Lu You ,  Minh Van Ngo

IPC分类号： H01L2348

CPC分类号： H01L21/76801 ,  H01L21/76807 ,  H01L21/76832 ,  H01L23/3171 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： Degradation of organic-doped silica glass low-k inter-layer dielectrics during fabrication is significantly reduced and resolution of submicron features is improved by the formation of dual nature capping/ARC layers on inter-layer dielectric films. The capping/ARC layer is formed in-situ on the organic-doped silica glass inter-layer dielectric. The in-situ formation of the capping/ARC layer provides a strongly adhered capping/ARC layer, formed with fewer processing steps than conventional capping and ARC layers.

摘要翻译： 通过在层间电介质膜上形成双重性质覆盖/ ARC层，在制造期间降低有机掺杂石英玻璃低k层间电介质的降解显着降低，并提高亚微米特征的分辨率。 在有机掺杂的石英玻璃层间电介质上原位形成封盖/ ARC层。 封盖/ ARC层的原位形成提供了强烈粘附的封盖/ ARC层，其形成与传统封盖和ARC层相比较少的处理步骤。

公开(公告)号：US06573179B1

公开(公告)日：2003-06-03

申请号：US09496223

申请日：2000-02-01

申请人： Pin-Chin C. Wang ,  Lu You

发明人： Pin-Chin C. Wang ,  Lu You

IPC分类号： H01L2144

CPC分类号： H01L21/76849 ,  H01L21/76856 ,  Y10S977/89

摘要： A strong interface is formed between an interconnect and an encapsulating layer to prevent the lateral drift of material from the interconnect along the bottom of the encapsulating layer. Diffusion barrier material is deposited on the top surface of the interconnect using a selective deposition process. The diffusion barrier material may be epitaxially grown from the interconnect during the selective deposition of the diffusion barrier material on the top surface of the interconnect to promote adhesion of the diffusion barrier material to the interconnect. An encapsulating layer is deposited on top of the diffusion barrier material. The diffusion barrier material and the encapsulating layer are comprised of a similar chemical element to promote adhesion of the diffusion barrier material to the encapsulating layer. The diffusion barrier material on the top surface of the interconnect prevents lateral drift of material comprising the interconnect along the encapsulating layer. When the layer of encapsulating dielectric is comprised of silicon nitride, a nitrided surface may be formed on top of the diffusion barrier material by exposing the top of the diffusion barrier material to nitrogen plasma before depositing the encapsulating layer of silicon nitride on top of the diffusion barrier material. The present invention may be used to particular advantage when the interconnect is a copper interconnect and when the layer of encapsulating layer is comprised of silicon nitride.

摘要翻译： 在互连和封装层之间形成强的界面，以防止材料沿封装层的底部从互连件的横向漂移。 使用选择性沉积工艺将扩散阻挡材料沉积在互连的顶表面上。 在扩散阻挡材料选择性地沉积在互连的顶表面上时，扩散阻挡材料可以从互连外延生长，以促进扩散阻挡材料与互连的粘附。 封装层沉积在扩散阻挡材料的顶部上。 扩散阻挡材料和封装层由类似的化学元素组成，以促进扩散阻挡材料与封装层的粘附。 互连顶表面上的扩散阻挡材料防止沿包封层包含互连的材料的横向漂移。 当封装电介质层由氮化硅组成时，可以在扩散阻挡材料的顶部上形成氮化表面，该方法是在将扩散阻挡材料的顶部暴露于氮等离子体之前，将氮化硅封装层沉积在扩散层顶部 阻隔材料。 当互连是铜互连并且当封装层由氮化硅构成时，本发明可以被用于特别的优点。

公开(公告)号：US06518646B1

公开(公告)日：2003-02-11

申请号：US09819615

申请日：2001-03-29

申请人： Dawn M. Hopper ,  Suzette K. Pangrle ,  Calvin T. Gabriel ,  Richard J. Huang ,  Lu You

发明人： Dawn M. Hopper ,  Suzette K. Pangrle ,  Calvin T. Gabriel ,  Richard J. Huang ,  Lu You

IPC分类号： H01L2358

CPC分类号： H01L21/76832 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76822 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： Strong adhesion to doped low-k inter-layer dielectrics is provided by varying the composition of dopant near the surface layers of the inter-layer dielectric. The concentration of dopant is gradually increased from about zero atomic % at the interface between the inter-layer dielectric and semiconductor substrate to improve adhesion of the inter-layer dielectric to the semiconductor substrate. The concentration of dopant at the upper surface of the inter-layer dielectric is gradually decreased to about zero atomic % at the upper surface of the inter-layer dielectric film in order to improve adhesion of additional layers to the inter-layer dielectric.

摘要翻译： 通过改变层间电介质的表面层附近掺杂剂的组成，提供了对掺杂低k层间电介质的强粘合性。 掺杂剂的浓度在层间电介质和半导体衬底之间的界面处从约零原子％逐渐增加，以提高层间电介质与半导体衬底的粘合性。 层间电介质的上表面的掺杂剂浓度在层间电介质膜的上表面逐渐降低至约零原子％，以提高附加层对层间电介质的附着力。

公开(公告)号：US06448594B1

公开(公告)日：2002-09-10

申请号：US09539307

申请日：2000-03-30

申请人： Maria C. Chan ,  Hao Fang ,  Lu You ,  Mark S. Chang ,  King Wai Kelwin Ko

发明人： Maria C. Chan ,  Hao Fang ,  Lu You ,  Mark S. Chang ,  King Wai Kelwin Ko

IPC分类号： H01L2976

CPC分类号： H01L21/823468 ,  H01L21/823425 ,  Y10S257/90

摘要： In a first aspect of the present invention, a semiconductor device is disclosed. The semiconductor device comprises at least two gate stacks, each gate stack having two sides and oxide spacers on each of the two sides of each of the at least two gate stacks, wherein at least one of the oxide spacers is triangular shaped. In a second aspect of the present invention, a method and system for processing a semiconductor device is disclosed. The method and system for processing a semiconductor comprise forming at least two gate stacks over a semiconductor substrate, depositing an oxide layer over the at least two gate stacks, and etching the oxide layer to form at least one oxide spacer in between the at least two gate stacks, wherein the at least one oxide spacer is triangular shape. Through the use the present invention, the voids that are created in the semiconductor device during conventional semiconductor processing are eliminated. This is accomplished by creating oxide spacers having a triangular shape when etching the oxide layer to form the oxide spacer. By creating a triangular shaped oxide spacer, subsequent layers of material can be deposited over the oxide spacer without creating voids in the semiconductor device. Accordingly, as a result of the use of the present invention, the oxide spacers are strengthened, which increases the reliability of the semiconductor device.

摘要翻译： 在本发明的第一方面中，公开了一种半导体器件。 半导体器件包括至少两个栅极堆叠，每个栅极堆叠体具有在所述至少两个栅极堆叠中的每一个的两侧上的两个侧面和氧化物间隔物，其中至少一个氧化物间隔物是三角形的。 在本发明的第二方面中，公开了一种用于处理半导体器件的方法和系统。 用于处理半导体的方法和系统包括在半导体衬底上形成至少两个栅极叠层，在所述至少两个栅极堆叠上沉积氧化物层，以及蚀刻氧化物层以在至少两个栅极堆叠之间形成至少一个氧化物间隔物 栅堆叠，其中所述至少一个氧化物间隔物是三角形的。 通过使用本发明，消除了在常规半导体处理期间在半导体器件中产生的空隙。 这通过在蚀刻氧化物层以形成氧化物间隔物时形成具有三角形形状的氧化物间隔物来实现。 通过产生三角形氧化物间隔物，随后的材料层可沉积在氧化物间隔物上，而不会在半导体器件中产生空隙。 因此，作为使用本发明的结果，氧化物间隔物被加强，这增加了半导体器件的可靠性。

公开(公告)号：US06410458B1

公开(公告)日：2002-06-25

申请号：US09494755

申请日：2000-01-31

申请人： Lu You ,  Dawn Hopper ,  John Jianshi Wang

发明人： Lu You ,  Dawn Hopper ,  John Jianshi Wang

IPC分类号： H01L2348

CPC分类号： H01L21/76835 ,  H01L21/76837 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention is a method and system for eliminating voids in a semiconductor device. The method comprises the steps of forming metal lines over a semiconductor substrate, forming a first oxide layer utilizing a high density plasma deposition technique, forming a second oxide layer utilizing a carbon free resin and forming a topside dielectric layer. Through the use of a method in accordance with the present invention, the voids that are created in the dielectric films during conventional semiconductor processing methodology are eliminated. The use of a high density plasma deposition technique provides a more directional deposition that can get between metal lines that are separated by smaller gaps. The dielectric films are thereby strengthened, which increases the reliability of the semiconductor device. Furthermore, by utilizing hydrogen silsesquiloxane instead of a conventional spin-on glass, there is no concern regarding carbon contamination since hydrogen silsesquiloxane doesn't contain carbon atoms.

摘要翻译： 本发明是用于消除半导体器件中的空隙的方法和系统。 该方法包括以下步骤：在半导体衬底上形成金属线，利用高密度等离子体沉积技术形成第一氧化物层，利用无碳树脂形成第二氧化物层并形成顶层电介质层。 通过使用根据本发明的方法，消除了在常规半导体处理方法中在电介质膜中产生的空隙。 使用高密度等离子体沉积技术提供了更多的定向沉积，其可以在由较小间隙分离的金属线之间获得。 因此，介电膜被加强，这增加了半导体器件的可靠性。 此外，通过使用氢硅氧烷代替常规旋涂玻璃，由于氢硅氧烷不含碳原子，因此不关心碳污染。

公开(公告)号：US06317642B1

公开(公告)日：2001-11-13

申请号：US09191438

申请日：1998-11-12

申请人： Lu You ,  Dawn Hopper ,  Christof Streck ,  John Pellerin ,  Richard J. Huang

发明人： Lu You ,  Dawn Hopper ,  Christof Streck ,  John Pellerin ,  Richard J. Huang

IPC分类号： G06F1900

CPC分类号： H01L21/6715 ,  B05D1/005

摘要： This invention describes improved apparatus and methods for spin-on deposition of semiconductor thin films. The improved apparatus provides for controlled temperature, pressure and gas compositions within the deposition chamber. The improved methods comprise dispensing of solutions containing thin film precursor via a moveable dispensing device and the careful regulation of the pattern of deposition of the precursor solution onto the wafer. The invention also comprises the careful regulation of deposition variables including dispensation time, wafer rpm, stop time and rates of wafer rotation. In one embodiment, the precursor solution is dispensed from the outer edge of the wafer toward the center. In alternative embodiments, processors regulate the movement of the dispensing arm and the precursor pump to provide an evenly dispensed layer of precursor solution. The invention also describes improved methods for evaporating solvents and curing thin films. The methods of this invention enable the production of spin-on thin films, which have more even film thickness and uniformity. The semiconductor thin films produced by the methods of this invention are useful for the manufacture of semiconductor devices comprising interlevel dielectric materials.

摘要翻译： 本发明描述了用于半导体薄膜的旋涂沉积的改进的装置和方法。 改进的装置提供沉积室内的受控温度，压力和气体组成。 改进的方法包括通过可移动的分配装置分配含有薄膜前体的溶液，以及仔细调节前体溶液沉积在晶片上的图案。 本发明还包括仔细调节沉积变量，包括分配时间，晶片转速，停止时间和晶片旋转速率。 在一个实施方案中，前体溶液从晶片的外边缘向中心分配。 在替代实施例中，处理器调节分配臂和前驱泵的运动，以提供均匀分配的前体溶液层。 本发明还描述了用于蒸发溶剂和固化薄膜的改进方法。 本发明的方法能够生产具有更均匀的膜厚度和均匀性的旋涂薄膜。 通过本发明的方法生产的半导体薄膜可用于制造包括层间电介质材料的半导体器件。