公开(公告)号：US06764949B2

公开(公告)日：2004-07-20

申请号：US10334392

申请日：2002-12-30

申请人： Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Darin Chan ,  Philip A. Fisher ,  Christopher F. Lyons ,  Mark S. Chang ,  Pei-Yuan Gao ,  Marilyn I. Wright ,  Lu You ,  Srikanteswara Dakshina-Murthy

发明人： Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Darin Chan ,  Philip A. Fisher ,  Christopher F. Lyons ,  Mark S. Chang ,  Pei-Yuan Gao ,  Marilyn I. Wright ,  Lu You ,  Srikanteswara Dakshina-Murthy

IPC分类号： H01L2144

CPC分类号： H01L21/32139 ,  H01L21/0332

摘要： A hardmask stack is comprised of alternating layers of doped amorphous carbon and undoped amorphous carbon. The undoped amorphous carbon layers serve as buffer layers that constrain the effects of compressive stress within the doped amorphous carbon layers to prevent delamination. The stack is provided with a top capping layer. The layer beneath the capping layer is preferably undoped amorphous carbon to reduce photoresist poisoning. An alternative hardmask stack is comprised of alternating layers of capping material and amorphous carbon. The amorphous carbon layers may be doped or undoped. The capping material layers serve as buffer layers that constrain the effects of compressive stress within the amorphous carbon layers to prevent delamination. The top layer of the stack is formed of a capping material. The layer beneath the top layer is preferably undoped amorphous carbon to reduce photoresist poisoning. The lowest layer of the hardmask stack is preferably amorphous carbon to facilitate easy removal of the hardmask stack from underlying materials by an ashing process.

公开(公告)号：US06773998B1

公开(公告)日：2004-08-10

申请号：US10445129

申请日：2003-05-20

申请人： Philip A. Fisher ,  Marina V. Plat ,  Chih-Yuh Yang ,  Christopher F. Lyons ,  Scott A. Bell ,  Douglas J. Bonser ,  Lu You ,  Srikanteswara Dakshina-Murthy

发明人： Philip A. Fisher ,  Marina V. Plat ,  Chih-Yuh Yang ,  Christopher F. Lyons ,  Scott A. Bell ,  Douglas J. Bonser ,  Lu You ,  Srikanteswara Dakshina-Murthy

IPC分类号： H01L21336

CPC分类号： H01L21/0276 ,  H01L21/0332 ,  H01L21/28123 ,  H01L21/31116 ,  H01L21/3146 ,  H01L21/32137 ,  H01L21/32139

摘要： A method for an integrated circuit includes the use of an amorphous carbon ARC mask. A layer of amorphous carbon material is deposited above a layer of conductive material, and a layer of anti-reflective coating (ARC) material is deposited over the layer of amorphous carbon material. The layer of amorphous carbon material and the layer of ARC material are etched to form a mask comprising an ARC material portion and an amorphous carbon portion. A feature may then be formed in the layer of conductive material by etching the layer of conductive material in accordance with the mask.

摘要翻译： 集成电路的方法包括使用无定形碳ARC掩模。 一层非晶碳材料沉积在导电材料层上方，并且一层抗反射涂层（ARC）材料沉积在无定形碳材料层上。 蚀刻无定形碳材料层和ARC材料层以形成包含ARC材料部分和无定形碳部分的掩模。 然后可以通过根据掩模蚀刻导电材料层而在导电材料层中形成特征。

公开(公告)号：US07268066B2

公开(公告)日：2007-09-11

申请号：US10922093

申请日：2004-08-19

申请人： Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Philip A. Fisher ,  Christopher F. Lyons

发明人： Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Philip A. Fisher ,  Christopher F. Lyons

IPC分类号： H01L21/4763

CPC分类号： H01L29/66477 ,  H01L21/28123 ,  H01L29/1045 ,  H01L29/1054 ,  H01L29/665

摘要： To reduce the width of a MOSFET gate, the gate is formed with a hardmask formed thereupon. An isotropic etch is then performed to trim the gate in order to reduce the width of the gate. The resulting gate may be formed with a width that is narrower than a minimum width achievable solely through conventional projection lithography techniques.

摘要翻译： 为了减小MOSFET栅极的宽度，栅极形成有在其上形成的硬掩模。 然后执行各向同性蚀刻以修剪栅极，以便减小栅极的宽度。 所形成的栅极可以形成为比仅通过常规投影光刻技术可实现的最小宽度窄的宽度。

公开(公告)号：US06849530B2

公开(公告)日：2005-02-01

申请号：US10334337

申请日：2002-12-30

申请人： Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Philip A. Fisher ,  Christopher F. Lyons

发明人： Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Philip A. Fisher ,  Christopher F. Lyons

IPC分类号： H01L21/28 ,  H01L21/4763

CPC分类号： H01L21/28123

摘要： To reduce the width of a MOSFET gate, the gate is formed with a hardmask formed thereupon. An isotropic etch is then performed to trim the gate in order to reduce the width of the gate. The resulting gate may be formed with a width that is narrower than a minimum width achievable solely through conventional projection lithography techniques.

公开(公告)号：US06864556B1

公开(公告)日：2005-03-08

申请号：US10335445

申请日：2002-12-31

申请人： Lu You ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Richard J. Huang ,  Christopher F. Lyons ,  Mark S. Chang ,  Marilyn I. Wright

发明人： Lu You ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Richard J. Huang ,  Christopher F. Lyons ,  Mark S. Chang ,  Marilyn I. Wright

IPC分类号： G03F7/09 ,  H01L21/033 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/47 ,  H01L31/0232

CPC分类号： H01L21/32139 ,  G03F7/091 ,  H01L21/0332 ,  H01L21/28123 ,  H01L29/785

摘要： A bottom anti-reflective coating comprising an organic polymer layer having substantially no nitrogen and a low compressive stress in relation to a polysilicon layer is employed as the lower layer of a bi-layer antireflective coating/hardmask structure to reduce deformation of a pattern to be formed in a patternable layer. The organic polymer layer is substantially transparent to visible radiation, enabling better detection of alignment marks during a semiconductor device fabrication process and improving overlay accuracy. The organic polymer layer provides excellent step coverage and may be advantageously used in the fabrication of structures such as FinFETs.

摘要翻译： 采用底层抗反射涂层，其包含基本上不含氮的有机聚合物层和相对于多晶硅层的低压缩应力作为双层抗反射涂层/硬掩模结构的下层，以减少图案的变形 形成在可图案层中。 有机聚合物层对可见辐射基本上是透明的，能够在半导体器件制造过程中更好地检测对准标记并提高覆盖精度。 有机聚合物层提供优异的台阶覆盖，并且可以有利地用于制造诸如FinFET的结构。

公开(公告)号：US07122455B1

公开(公告)日：2006-10-17

申请号：US10790567

申请日：2004-03-01

申请人： Christopher F. Lyons ,  Marina V. Plat ,  Srikanteswara Dakshina-Murthy ,  Scott A. Bell ,  Cyrus E. Tabery

发明人： Christopher F. Lyons ,  Marina V. Plat ,  Srikanteswara Dakshina-Murthy ,  Scott A. Bell ,  Cyrus E. Tabery

IPC分类号： H01L21/3205

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28035 ,  H01L21/28123 ,  Y10S438/942 ,  Y10S438/947

摘要： For patterning an IC (integrated circuit) material, a rigid organic under-layer is formed over the IC material, and the rigid organic under-layer is patterned to form a rigid organic mask structure. In addition, the rigid organic mask structure is trimmed to lower a critical dimension of the rigid organic mask structure beyond the limitations of traditional BARC mask structures. Any portion of the IC material not under the rigid organic mask structure is etched away to form an IC structure.

摘要翻译： 为了图案化IC（集成电路）材料，在IC材料之上形成刚性有机底层，并且将刚性有机底层图案化以形成刚性有机掩模结构。 此外，修剪刚性有机掩模结构以降低刚性有机掩模结构的临界尺寸超出传统BARC掩模结构的限制。 不会在刚性有机掩模结构下面的IC材料的任何部分被蚀刻掉以形成IC结构。

公开(公告)号：US07052921B1

公开(公告)日：2006-05-30

申请号：US10934192

申请日：2004-09-03

申请人： Marina V. Plat ,  Bhanwar Singh ,  Calvin T. Gabriel ,  Christopher F. Lyons ,  Scott A. Bell ,  Ramkumar Subramanian ,  Srikanteswara Dakshina-Murthy

发明人： Marina V. Plat ,  Bhanwar Singh ,  Calvin T. Gabriel ,  Christopher F. Lyons ,  Scott A. Bell ,  Ramkumar Subramanian ,  Srikanteswara Dakshina-Murthy

IPC分类号： H01L21/66

CPC分类号： G03F7/70625 ,  G03F7/70608 ,  H01L22/12

摘要： The present invention uses in situ scatterometry to determine if a defect (e.g., photoresist erosion, photoresist bending and pattern collapse) is present on a wafer. In one embodiment, in situ scatterometry is used to detect a pattern integrity defect associated with the layer of photoresist. In situ scatterometry produces diffraction data associated with the thickness of the photoresist patterned mask. This data is compared to a model of diffraction data associated with a suitable photoresist thickness. If the measured diffraction data is within an acceptable range, the next step of the photolithography process is carried out. However, if the measured thickness is outside of the suitable range, a defect is detected, and the wafer may be sent for re-working or re-patterned prior to main etch, thereby preventing unnecessary wafer scrap. Another aspect of the present invention allows for a feedback control mechanism to alter a physical parameter of the photolithographic process based upon the in situ scatterometry measurements.

摘要翻译： 本发明使用原位散射法来确定晶片上是否存在缺陷（例如，光致抗蚀剂侵蚀，光致抗蚀剂弯曲和图案崩溃）。 在一个实施例中，原位散射法用于检测与光致抗蚀剂层相关联的图案完整性缺陷。 原位散射法产生与光致抗蚀剂图案掩模的厚度相关的衍射数据。 将该数据与与合适的光致抗蚀剂厚度相关联的衍射数据的模型进行比较。 如果测量的衍射数据在可接受的范围内，则进行光刻工艺的下一步骤。 然而，如果测量的厚度在合适的范围之外，则检测到缺陷，并且可以在主蚀刻之前将晶片发送用于再加工或重新图案化，从而防止不必要的晶片废料。 本发明的另一方面允许反馈控制机制基于原位散射测量来改变光刻工艺的物理参数。

公开(公告)号：US06825114B1

公开(公告)日：2004-11-30

申请号：US10424675

申请日：2003-04-28

申请人： Philip A. Fisher ,  Christopher F. Lyons ,  Srikanteswara Dakshina-Murthy

发明人： Philip A. Fisher ,  Christopher F. Lyons ,  Srikanteswara Dakshina-Murthy

IPC分类号： H01L2144

CPC分类号： H01L21/0332 ,  H01L21/32139 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a fuse for use in an integrated circuit using an amorphous carbon mask includes providing a mask material layer comprising amorphous carbon over a conductive layer. The mask material layer is doped with nitrogen, and an anti-reflective coating (ARC) feature is formed over the mask layer. A portion of the mask material layer is removed according to the ARC feature to form a mask, and the ARC feature is removed to form a warped mask. The conductive layer is patterned according to the warped mask, the warped mask is removed, and a silicide layer is provided over the patterned conductive layer.

摘要翻译： 使用非晶碳掩模形成用于集成电路的熔丝的方法包括在导电层上提供包含无定形碳的掩模材料层。 掩模材料层掺杂有氮，并且在掩模层上形成抗反射涂层（ARC）特征。 根据ARC特征去除掩模材料层的一部分以形成掩模，并且去除ARC特征以形成翘曲的掩模。 根据翘曲的掩模对导电层进行图案化，去除翘曲的掩模，并且在图案化的导电层上提供硅化物层。

公开(公告)号：US06989332B1

公开(公告)日：2006-01-24

申请号：US10217730

申请日：2002-08-13

申请人： Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Christopher F. Lyons

发明人： Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Christopher F. Lyons

IPC分类号： H01L21/302

CPC分类号： H01L21/32139 ,  C23C16/26 ,  C23C16/56 ,  H01L21/0332

摘要： A method of manufacturing an integrated circuit includes providing a layer of polysilicon material above a semiconductor substrate. A layer of amorphous carbon is provided above the layer of polysilicon material and inert ions are implanted into the amorphous carbon layer. The layer of amorphous carbon is patterned to form an amorphous carbon mask, and a feature is formed in the layer of polysilicon according to the amorphous carbon mask.

摘要翻译： 一种制造集成电路的方法包括在半导体衬底之上提供多晶硅材料层。 在多晶硅材料层上方提供无定形碳层，惰性离子注入到无定形碳层中。 将非晶碳层图案化以形成无定形碳掩模，并且根据无定形碳掩模在多晶硅层中形成特征。

公开(公告)号：US06689541B1

公开(公告)日：2004-02-10

申请号：US09884182

申请日：2001-06-19

申请人： Scott A. Bell ,  Todd P. Lukanc ,  Christopher F. Lyons ,  Marina V. Plat ,  Ramkumar Subramanian

发明人： Scott A. Bell ,  Todd P. Lukanc ,  Christopher F. Lyons ,  Marina V. Plat ,  Ramkumar Subramanian

IPC分类号： G03C500

CPC分类号： G03F7/38 ,  G03F7/265 ,  G03F7/40

摘要： In a process for forming a photoresist mask, a photoresist layer is applied to a substrate. A silyated layer is formed in the photoresist layer. The features of the silyated area correspond to the features of a photoresist mask to be formed. The photoresist layer is then etched to form a photoresist base beneath the silyated area. The photoresist base is etched to remove material from its sides such that it becomes narrower than the silyated area. The silyated area is then removed, leaving a photoresist mask on the substrate.

摘要翻译： 在形成光致抗蚀剂掩模的工艺中，将光致抗蚀剂层施加到基底上。 在光致抗蚀剂层中形成硅化层。 硅酸盐化区域的特征对应于要形成的光致抗蚀剂掩模的特征。 然后蚀刻光致抗蚀剂层以在硅化区域下方形成光致抗蚀剂基底。 蚀刻光致抗蚀剂基底以从其侧面去除材料，使得它比斯里芬特区域变窄。 然后除去硅酸盐化区域，在基材上留下光刻胶掩模。