利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

96 条记录 (耗时 0.019 秒)

    Semiconductor devices with dual nature capping/ARC layers on fluorine doped silica glass inter-layer dielectrics and method of forming capping/ARC layers
    1.
    发明授权
    Semiconductor devices with dual nature capping/ARC layers on fluorine doped silica glass inter-layer dielectrics and method of forming capping/ARC layers 有权
    在氟掺杂石英玻璃层间电介质上具有双重性质封装/ ARC层的半导体器件和形成封盖/ ARC层的方法

    公开(公告)号：US06576545B1

    公开(公告)日：2003-06-10

    申请号：US09819987

    申请日：2001-03-29

    申请人： Dawn M. Hopper ,  Lu You ,  Minh Van Ngo

    发明人： Dawn M. Hopper ,  Lu You ,  Minh Van Ngo

    IPC分类号： H01L214763

    CPC分类号： H01L21/76829 ,  H01L21/76807

    摘要： Degradation of fluorine-doped silica glass low-k inter-layer dielectrics during fabrication is significantly reduced and resolution of submicron features is improved by the formation of dual nature capping/ARC layers on inter-layer dielectric films. The capping/ARC layer is formed in-situ on a fluorine-doped silica glass inter-layer dielectric. The in-situ formation of the capping/ARC layer provides a strongly adhered capping/ARC layer, formed with fewer processing steps than conventional capping and ARC layers.

    摘要翻译： 通过在层间电介质膜上形成双重性能覆盖/ ARC层，制造过程中氟掺杂二氧化硅玻璃低k层间电介质的退化显着降低，亚微米特征的分辨率得到改善。 封盖/ ARC层在氟掺杂石英玻璃层间电介质上原位形成。 封盖/ ARC层的原位形成提供了强烈粘附的封盖/ ARC层，其形成与传统封盖和ARC层相比较少的处理步骤。

    Use of sion for preventing copper contamination of dielectric layer
    3.
    发明授权
    Use of sion for preventing copper contamination of dielectric layer 失效
    使用硫化物防止介电层的铜污染

    公开(公告)号：US06576982B1

    公开(公告)日：2003-06-10

    申请号：US09776746

    申请日：2001-02-06

    申请人： Lu You ,  Dawn M. Hopper ,  Minh Van Ngo

    发明人： Lu You ,  Dawn M. Hopper ,  Minh Van Ngo

    IPC分类号： H01L2358

    CPC分类号： H01L21/76831 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76813 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes a first metallization layer, a first diffusion barrier layer, a first etch stop layer, a dielectric layer and a via extending through the dielectric layer, the first etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization layer. The first etch stop layer is disposed over the first diffusion barrier layer, and the dielectric layer is disposed over the first etch stop layer. The via can also have rounded corners. A sidewall diffusion barrier layer can be disposed on sidewalls of the via, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. The first etch stop layer can be formed from silicon oxynitride. A method of manufacturing the semiconductor device is also disclosed.

    摘要翻译： 半导体器件包括第一金属化层，第一扩散阻挡层，第一蚀刻停止层，介电层和延伸穿过介电层的通孔，第一蚀刻停止层和第一扩散阻挡层。 第一扩散阻挡层设置在第一金属化层上。 第一蚀刻停止层设置在第一扩散阻挡层上，并且电介质层设置在第一蚀刻停止层上。 通孔也可以有圆角。 侧壁扩散阻挡层可以设置在通孔的侧壁上，并且侧壁扩散阻挡层由与第一扩散阻挡层相同的材料形成。 第一蚀刻停止层可以由氮氧化硅形成。 还公开了制造半导体器件的方法。

    Conformal liner for gap-filling
    6.
    发明申请
    Conformal liner for gap-filling 审中-公开
    用于间隙填充的保形衬套

    公开(公告)号：US20080096364A1

    公开(公告)日：2008-04-24

    申请号：US11582442

    申请日：2006-10-18

    申请人： Erik Wilson ,  Minh-Van Ngo ,  Hieu Pham ,  Robert Huertas ,  Lu You ,  Hirokazu Tokuno ,  Alexander Nickel ,  Minh Tran

    发明人： Erik Wilson ,  Minh-Van Ngo ,  Hieu Pham ,  Robert Huertas ,  Lu You ,  Hirokazu Tokuno ,  Alexander Nickel ,  Minh Tran

    IPC分类号： H01L21/76

    CPC分类号： H01L21/823468 ,  H01L21/76829 ,  H01L21/76837 ,  H01L21/823437

    摘要： Gap filling between features which are closely spaced is significantly improved by initially depositing a thin conformal layer followed by depositing a layer of gap filling dielectric material. Embodiments include depositing a thin conformal layer of silicon nitride or silicon oxide, as by atomic layer deposition or pulsed layer deposition, into the gap between adjacent gate electrode structures such that it flows into undercut regions of dielectric spacers on side surfaces of the gate electrode structures, and then depositing a layer of BPSG or P-HDP oxide on the thin conformal layer into the gap. Embodiments further include depositing the layers at a temperature less than 430° C., as by depositing a P-HDP oxide after depositing the conformal liner when the gate electrode structures include a layer of nickel silicide.

    摘要翻译： 通过初始沉积薄的共形层，然后沉积一层间隙填充电介质材料，密切间隔的特征之间的间隙填充显着改善。 实施例包括通过原子层沉积或脉冲层沉积将氮化硅或氧化硅的薄保形层沉积到相邻栅电极结构之间的间隙中，使得其流到栅电极结构的侧表面上的电介质间隔物的底切区域 ，然后在薄的共形层上沉积一层BPSG或P-HDP氧化物到间隙中。 实施例还包括在低于430℃的温度下沉积层，如通过在栅极电极结构包括硅化镍层沉积保形衬垫之后沉积P-HDP氧化物。

    Silane treatment of low dielectric constant materials in semiconductor device manufacturing
    7.
    发明授权
    Silane treatment of low dielectric constant materials in semiconductor device manufacturing 有权
    半导体器件制造中低介电常数材料的硅烷处理

    公开(公告)号：US06566283B1

    公开(公告)日：2003-05-20

    申请号：US10073068

    申请日：2002-02-12

    申请人： Suzette K. Pangrle ,  Minh Van Ngo ,  Dawn Hopper ,  Lu You

    发明人： Suzette K. Pangrle ,  Minh Van Ngo ,  Dawn Hopper ,  Lu You

    IPC分类号： H01L2131

    CPC分类号： H01L21/76831 ,  H01L21/31058 ,  H01L21/76802 ,  H01L21/76826

    摘要： Improved dielectric layers are formed by surface treating the dielectric layer with a silane plasma prior to forming a subsequent layer thereon. Embodiments include forming a trench in a low k dielectric layer and modifying the side surfaces of the trench by subjecting the dielectric to a silane plasma produced in a PECVD chamber. A conductive feature is formed by depositing a conformal barrier layer on the low k dielectric including the treated side surfaces of the dielectric and depositing a conductive layer within the trench.

    摘要翻译： 通过在形成其之后的层之前用硅烷等离子体表面处理电介质层来形成改进的电介质层。 实施例包括在低k电介质层中形成沟槽，并通过对电介质进行在PECVD室中产生的硅烷等离子体来修饰沟槽的侧表面。 通过在包括电介质处理的侧表面的低k电介质上沉积共形阻挡层并在沟槽内沉积导电层来形成导电特征。

    Method of improving adhesion of capping layers to cooper interconnects
    8.
    发明授权
    Method of improving adhesion of capping layers to cooper interconnects 有权
    提高封盖层对铜互连的粘附性的方法

    公开(公告)号：US06383925B1

    公开(公告)日：2002-05-07

    申请号：US09497850

    申请日：2000-02-04

    申请人： Minh Van Ngo ,  Lu You ,  Robert A. Huertas ,  Ercan Adem

    发明人： Minh Van Ngo ,  Lu You ,  Robert A. Huertas ,  Ercan Adem

    IPC分类号： H01L2144

    CPC分类号： H01L21/76838 ,  H01L21/76834 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The adhesion of a barrier or capping layer to a Cu or Cu alloy interconnect member is significantly enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member, after CMP, in a reaction chamber with a plasma containing ammonia and nitrogen for a brief period of time to reduce the surface oxide and then introducing silane into the reaction chamber to deposit the barrier layer, e.g., silicon nitride, under high density plasma conditions in the presence of nitrogen. The presence of nitrogen during plasma oxide layer reduction and plasma barrier layer deposition significantly improves adhesion of the barrier layer to the Cu or Cu alloy surface.

    摘要翻译： 通过在具有氨和氮气的等离子体的反应室中处理Cu或Cu合金互连构件的CMP暴露表面之后，通过将Cu或Cu合金互连构件的阻挡层或覆盖层的粘合性显着提高， 一段时间以减少表面氧化物，然后将硅烷引入反应室，以在氮气存在下在高密度等离子体条件下沉积阻挡层，例如氮化硅。 在等离子体氧化物层还原和等离子体阻挡层沉积期间氮的存在显着提高了阻挡层对Cu或Cu合金表面的粘附性。

    Using thin undoped TEOS with BPTEOS ILD or BPTEOS ILD alone to improve charge loss and contact resistance in multi bit memory devices
    10.
    发明授权
    Using thin undoped TEOS with BPTEOS ILD or BPTEOS ILD alone to improve charge loss and contact resistance in multi bit memory devices 有权
    单独使用BPTEOS ILD或BPTEOS ILD的薄的未掺杂TEOS来改善多位存储器件中的电荷损耗和接触电阻

    公开(公告)号：US07157335B1

    公开(公告)日：2007-01-02

    申请号：US10917562

    申请日：2004-08-13

    申请人： Ning Cheng ,  Minh Van Ngo ,  Hirokazu Tokuno ,  Lu You ,  Angela T. Hui ,  Yi He ,  Brian Mooney ,  Jean Yei-Mei Yang ,  Mark T. Ramsbey

    发明人： Ning Cheng ,  Minh Van Ngo ,  Hirokazu Tokuno ,  Lu You ,  Angela T. Hui ,  Yi He ,  Brian Mooney ,  Jean Yei-Mei Yang ,  Mark T. Ramsbey

    IPC分类号： H01L21/336

    CPC分类号： H01L27/115 ,  H01L27/11568

    摘要： The present invention facilitates dual bit memory devices and operation of dual bit memory device by providing systems and methods that employ a relatively thin undoped TEOS liner during fabrication, instead of a relatively thick TEOS layer that is conventionally used. Employment of the relatively thin liner facilitates dual bit memory device operation by mitigating charge loss and contact resistance while providing protection against unwanted dopant diffusion. The present invention includes utilizing a relatively thin undoped TEOS liner that is formed on wordlines and portions of a charge trapping dielectric layer. The relatively thin undoped TEOS liner is formed with a thickness of less than about 400 Angstroms so that contact resistance and charge loss are improved and yet providing suitable protection for operation of the device. Additionally, the present invention includes foregoing with an undoped TEOS liner altogether.

    摘要翻译： 本发明通过提供在制造期间使用相对薄的未掺杂TEOS衬垫的系统和方法而不是通常使用的相对较厚的TEOS层来便于双位存储器件和双位存储器件的操作。 使用相对薄的衬垫通过减轻电荷损失和接触电阻而提供双位存储器件操作，同时提供防止不期望的掺杂剂扩散的保护。 本发明包括利用形成在字线和电荷捕获电介质层的部分上的相对薄的未掺杂的TEOS衬垫。 相对薄的未掺杂的TEOS衬垫形成有小于约400埃的厚度，使得接触电阻和电荷损失得到改善，并且为器件的操作提供适当的保护。 此外，本发明包括前述的未掺杂的TEOS衬垫。