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    THREE-DIMENSIONAL MEMORY ARRAY
    81.
    发明申请
    THREE-DIMENSIONAL MEMORY ARRAY 审中-公开

    公开(公告)号：US20200176512A1

    公开(公告)日：2020-06-04

    申请号：US16785026

    申请日：2020-02-07

    Applicant: Micron Technology, Inc.

    Inventor： Anna Maria Conti ,  Andrea Redaelli ,  Agostino Pirovano

    IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

    Abstract: An example three-dimensional (3-D) memory array includes a first plurality of conductive lines separated from one other by an insulation material, a second plurality of conductive lines, and a plurality of pairs of conductive pillars arranged to extend substantially perpendicular to the first plurality of conductive lines and the second plurality of conductive lines. The conductive pillars of each respective pair are coupled to a same conductive line of the second plurality of conductive lines. A storage element material is formed partially around the conductive pillars of each respective pair.

    Self-selecting memory array with horizontal bit lines
    82.
    发明授权
    Self-selecting memory array with horizontal bit lines 有权

    公开(公告)号：US10593399B2

    公开(公告)日：2020-03-17

    申请号：US15925536

    申请日：2018-03-19

    Applicant: Micron Technology, Inc.

    Inventor： Lorenzo Fratin ,  Fabio Pellizzer ,  Agostino Pirovano ,  Russell L. Meyer

    IPC: G11C13/00 ,  H01L23/528

    Abstract: Methods, systems, and devices for self-selecting memory with horizontal access lines are described. A memory array may include first and second access lines extending in different directions. For example, a first access line may extend in a first direction, and a second access line may extend in a second direction. At each intersection, a plurality of memory cells may exist, and each plurality of memory cells may be in contact with a self-selecting material (SSM). Further, a dielectric material may be positioned between a first plurality of memory cells and a second plurality of memory cells in at least one direction. each cell group (e.g., a first and second plurality of memory cells) may be in contact with one of the first access lines and second access lines, respectively.

    Memory cells with asymmetrical electrode interfaces
    83.
    发明授权
    Memory cells with asymmetrical electrode interfaces 有权

    公开(公告)号：US10541364B2

    公开(公告)日：2020-01-21

    申请号：US15893108

    申请日：2018-02-09

    Applicant: Micron Technology, Inc.

    Inventor： Agostino Pirovano ,  Kolya Yastrebenetsky ,  Anna Maria Conti ,  Fabio Pellizzer

    IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

    Abstract: Methods, systems, and devices for memory cells with asymmetrical electrode interfaces are described. A memory cell with asymmetrical electrode interfaces may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a top surface area in contact with a top electrode and a bottom surface area in contact with a bottom electrode, where the top surface area in contact with the top electrode is a different size than the bottom surface area in contact with the bottom electrode.

    Self-aligned memory decks in cross-point memory arrays
    84.
    发明授权
    Self-aligned memory decks in cross-point memory arrays 有权

    公开(公告)号：US10510957B2

    公开(公告)日：2019-12-17

    申请号：US15660829

    申请日：2017-07-26

    Applicant: Micron Technology, Inc.

    Inventor： Agostino Pirovano ,  Fabio Pellizzer ,  Anna Maria Conti ,  Andrea Redaelli ,  Innocenzo Tortorelli

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A multi-layer memory device with an array having multiple memory decks of self-selecting memory cells is provided in which N memory decks may be fabricated with N+1 mask operations. The multiple memory decks may be self-aligned and certain manufacturing operations may be performed for multiple memory decks at the same time. For example, patterning a bit line direction of a first memory deck and a word line direction in a second memory deck above the first memory deck may be performed in a single masking operation, and both decks may be etched in a same subsequent etching operation. Such techniques may provide efficient fabrication which may allow for enhanced throughput, additional capacity, and higher yield for fabrication facilities relative to processing techniques in which each memory deck is processed using two or more mask and etch operations per memory deck.

    THREE DIMENSIONAL MEMORY ARRAY
    86.
    发明申请
    THREE DIMENSIONAL MEMORY ARRAY 审中-公开

    公开(公告)号：US20190341425A1

    公开(公告)日：2019-11-07

    申请号：US16513797

    申请日：2019-07-17

    Applicant: Micron Technology, Inc.

    Inventor： Fabio Pellizzer ,  Innocenzo Tortorelli ,  Agostino Pirovano ,  Andrea Redaelli

    IPC: H01L27/24 ,  G11C13/00 ,  H01L45/00

    Abstract: The present disclosure includes three dimensional memory arrays, and methods of processing the same. A number of embodiments include a plurality of conductive lines separated from one other by an insulation material, a plurality of conductive extensions arranged to extend substantially perpendicular to the plurality of conductive lines, and a storage element material formed around each respective one of the plurality of conductive extensions and having two different contacts with each respective one of the plurality of conductive lines, wherein the two different contacts with each respective one of the plurality of conductive lines are at two different ends of that respective conductive line.

    ENHANCING NUCLEATION IN PHASE-CHANGE MEMORY CELLS
    87.
    发明申请
    ENHANCING NUCLEATION IN PHASE-CHANGE MEMORY CELLS 审中-公开

    公开(公告)号：US20190295642A1

    公开(公告)日：2019-09-26

    申请号：US16372010

    申请日：2019-04-01

    Applicant: Micron Technology, Inc.

    Inventor： Agostino Pirovano ,  Fabio Pellizzer ,  Anna Maria Conti ,  Davide Fugazza ,  Johannes A. Kalb

    IPC: G11C13/00

    Abstract: Various embodiments disclosed herein comprise methods and apparatuses for placing phase-change memory (PCM) cells of a memory array into a temperature regime where nucleation probability of the PCM cells is enhanced prior to applying a subsequent SET programming signal. In one embodiment, the method includes applying a nucleation signal to the PCM cells to form nucleation sites within the memory array where the nucleation signal has a non-zero rising-edge. A programming signal is subsequently applied to achieve a desired level of crystallinity within selected ones of the plurality of PCM cells. Additional methods and apparatuses are also described.

    MATERIAL IMPLICATION OPERATIONS IN MEMORY
    89.
    发明申请
    MATERIAL IMPLICATION OPERATIONS IN MEMORY 审中-公开

    公开(公告)号：US20190198105A1

    公开(公告)日：2019-06-27

    申请号：US15853803

    申请日：2017-12-24

    Applicant: Micron Technology, Inc.

    Inventor： Agostino Pirovano

    IPC: G11C13/00

    CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/003 ,  G11C2213/30 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148

    Abstract: The present disclosure includes apparatuses and methods for material implication operations in memory. An example apparatus may include a plurality of memory cells coupled to a first access line and a plurality of second access lines, and a controller coupled to the plurality of memory cells. The controller of the example apparatus may be configured to apply a first signal to the first access line, and while the first signal is being applied to the first access line, apply a second signal to a first of the plurality of memory cells via another respective one of the plurality of second access lines and apply a third signal to a second of the plurality of memory cells via another respective one of the plurality of second access lines. The material implication operation may be performed as a result of the signals (e.g., first, second, and third signals) applied and a result of the material implication operation is stored on the second of the plurality of memory cells subsequent to the application of the third signal.

    Enhancing nucleation in phase-change memory cells
    90.
    发明授权
    Enhancing nucleation in phase-change memory cells 有权

    公开(公告)号：US10276235B2

    公开(公告)日：2019-04-30

    申请号：US15980480

    申请日：2018-05-15

    Applicant: Micron Technology, Inc.

    Inventor： Agostino Pirovano ,  Fabio Pellizzer ,  Anna Maria Conti ,  Davide Fugazza ,  Johannes A. Kalb

    IPC: G11C13/00 ,  G11C7/04

    Abstract: Various embodiments disclosed herein comprise methods and apparatuses for placing phase-change memory (PCM) cells of a memory array into a temperature regime where nucleation probability of the PCM cells is enhanced prior to applying a subsequent SET programming signal. In one embodiment, the method includes applying a nucleation signal to the PCM cells to form nucleation sites within the memory array where the nucleation signal has a non-zero rising-edge. A programming signal is subsequently applied to achieve a desired level of crystallinity within selected ones of the plurality of PCM cells. Additional methods and apparatuses are also described.

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