公开(公告)号：US20220334915A1

公开(公告)日：2022-10-20

申请号：US17857700

申请日：2022-07-05

Applicant: Micron Technology, Inc.

Inventor： Martin Brox ,  Peter Mayer ,  Wolfgang Anton Spirkl ,  Thomas Hein ,  Michael Dieter Richter ,  Timothy M. Hollis ,  Roy E. Greeff

IPC: G06F11/10 ,  G06F11/16 ,  G06F12/02

Abstract: Methods, systems, and devices for channel modulation for a memory device are described. A system may include a memory device and a host device coupled with the memory device. The system may be configured to communicate a first signal modulated using a first modulation scheme and communicate a second signal that is based on the first signal and that is modulated using a second modulation scheme. The first modulation scheme may include a first quantity of voltage levels that span a first range of voltages, and the second modulation scheme may include a second quantity of voltage levels that span a second range of voltages different than (e.g., smaller than) the first range of voltages. The first signal may include write data carried over a data channel, and the second signal may include error detection information based on the write data that is carried over an error detection channel.

公开(公告)号：US20220329464A1

公开(公告)日：2022-10-13

申请号：US17225602

申请日：2021-04-08

Applicant: Micron Technology, Inc.

Inventor： Timothy M. Hollis

IPC: H04L25/03 ,  H04L25/02 ,  H04L1/16 ,  H04L1/00

Abstract: Systems and methods for implementation of modified decision feedback equalization. In one embodiment, a method, includes sweeping a reference voltage signal across a set of voltages to find a center point of an eye diagram, determining whether an asymmetry is present in the eye diagram relative to the center point of the eye diagram, and when an asymmetry is determined to be present, generating a control signal to select a mode of decision feedback equalization to be applied to an input data bit.

公开(公告)号：US11409595B2

公开(公告)日：2022-08-09

申请号：US16744025

申请日：2020-01-15

Applicant: Micron Technology, Inc.

Inventor： Martin Brox ,  Peter Mayer ,  Wolfgang Anton Spirkl ,  Thomas Hein ,  Michael Dieter Richter ,  Timothy M. Hollis ,  Roy E. Greeff

IPC: G06F11/00 ,  H03M13/00 ,  G06F11/10 ,  G06F11/16 ,  G06F12/02

Abstract: Methods, systems, and devices for channel modulation for a memory device are described. A system may include a memory device and a host device coupled with the memory device. The system may be configured to communicate a first signal modulated using a first modulation scheme and communicate a second signal that is based on the first signal and that is modulated using a second modulation scheme. The first modulation scheme may include a first quantity of voltage levels that span a first range of voltages, and the second modulation scheme may include a second quantity of voltage levels that span a second range of voltages different than (e.g., smaller than) the first range of voltages. The first signal may include write data carried over a data channel, and the second signal may include error detection information based on the write data that is carried over an error detection channel.

公开(公告)号：US20220224570A1

公开(公告)日：2022-07-14

申请号：US17149364

申请日：2021-01-14

Applicant: Micron Technology, Inc.

Inventor： Timothy M. Hollis

IPC: H04L25/03

Abstract: Methods, systems, and devices for techniques for time-variable decision feedback equalization are described. A memory device may be coupled with a host device using one or more conductive lines. A receiver may receive a signal transmitted from another device over a conductive line. The receiver may include a decision circuit used to determine voltages of the received signal based on the received signal and a feedback signal and output an output signal. The receiver may include a variable time-delay circuit configured to output delayed signals that are delayed versions of the output signal and a gain circuit that is configured to scale the delayed signals to generate the feedback signal. The variable time-delay circuit may include delay elements having variable delay parameters. The receiver may be coupled with a memory array that stores the information conveyed by the output signal.

公开(公告)号：US20220206717A1

公开(公告)日：2022-06-30

申请号：US17562560

申请日：2021-12-27

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim ,  Hyun Yoo Lee ,  Timothy M. Hollis ,  Dong Soon Lim

IPC: G06F3/06

Abstract: Described apparatuses and methods enable communication between a host device and a memory device to establish relative delays between different data lines. If data signals propagate along a bus with the same timing, simultaneous switching output (SSO) and crosstalk can adversely impact channel timing budget parameters. An example system includes an interconnect having multiple data lines that couple the host device to the memory device. In example operations, the host device can transmit to the memory device a command indicative of a phase offset between two or more data lines of the multiple data lines. The memory device can implement the command by transmitting or receiving signals via the interconnect with different relative phase offsets between data lines. The host device (e.g., a memory controller) can determine appropriate offsets for a given apparatus. Lengths of the offsets can vary. Further, a system can activate the phase offsets based on frequency.

公开(公告)号：US20220005512A1

公开(公告)日：2022-01-06

申请号：US17360922

申请日：2021-06-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Matthew B. Leslie ,  Timothy M. Hollis ,  Roy E. Greeff

IPC: G11C7/10 ,  H04L25/03

Abstract: Embodiments of the disclosure include signal processing methods to reduce crosstalk between signal lines of a channel bus using feed forward equalizers (FFEs) configured smear pulse response energy transmitted on signal lines of the channel to reduce pulse edge rates. The coefficients for the FFE may be based on crosstalk interference characteristics. Smearing or spreading pulse response energy across a longer time period using a FFE increases inter-symbol interference (ISI). To counter increased inter-symbol interference caused by smearing pulse response energy, receivers configured to recover symbol data transmitted on the channel bus may each include respective decision-feedback equalizers (DFEs) that are configured to filter ISI from transmitted symbols based on previous symbol decisions of the channel. The combination of the FFE configured to smear pulse responses and the DFE to filter ISI may improve data eye quality for recovery of transmitted data on a channel bus when crosstalk dominates noise.

公开(公告)号：US20210375738A1

公开(公告)日：2021-12-02

申请号：US17334447

申请日：2021-05-28

Applicant: Micron Technology, Inc.

Inventor： David K. Ovard ,  Thomas Hein ,  Timothy M. Hollis ,  Walter L. Moden

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: Apparatuses may include a device substrate including a microelectronic device and bond pads proximate to an active surface of the device substrate. A package substrate may be secured to the device substrate, the package substrate configured to route signals to and from the bond pads. A ball grid array may be supported on, and electrically connected to, the package substrate. Each ball positioned and configured to carry a high-bandwidth data signal or a high-frequency clock signal may be located laterally or longitudinally adjacent to no more than one other ball of the ball grid array configured to carry a high-bandwidth data signal or a high-frequency clock signal. Each ball positioned and configured to carry a high-bandwidth data signal may be located only diagonally adjacent to any other balls configured to carry a high-bandwidth data signal or a high-frequency clock signal.

公开(公告)号：US11087804B2

公开(公告)日：2021-08-10

申请号：US16711359

申请日：2019-12-11

Applicant: Micron Technology, Inc.

Inventor： Timothy M. Hollis

IPC: G11C7/10 ,  H01L25/065 ,  H01L23/48 ,  G06F13/16 ,  G11C7/22 ,  G11C11/408 ,  G11C11/22

Abstract: Methods, systems, and apparatuses for a memory device that is configurable based on the type of substrate used to couple the memory device with a host device are described. The reconfigurable memory device may include a plurality of components for different configurations. Various components of the reconfigurable memory die may be activated/deactivated based on a type of substrate used in the memory device. The memory device may include an input/output (I/O) interface that is variously configurable. A first configuration may cause the memory device to communicate signals modulated using a first modulation scheme across a channel of a first width. A second configuration may cause the memory device to communicate signals modulated using a second modulation scheme across a channel of a second width. The I/O interface may include one or more switching components to selectively couple pins of a channel together and/or selectively couple components to various pins.

公开(公告)号：US20210035617A1

公开(公告)日：2021-02-04

申请号：US16530739

申请日：2019-08-02

Applicant: Micron Technology, Inc.

Inventor： Eric J. Stave ,  George E. Pax ,  Yogesh Sharma ,  Gregory A. King ,  Chan H. Yoo ,  Randon K. Richards ,  Timothy M. Hollis

IPC: G11C7/22 ,  G11C7/10 ,  G11C16/10

Abstract: Systems, apparatuses, and methods for operating a memory device or devices are described. A memory device or module may introduce latency in commands to coordinate operations at the device or to improve timing or power consumption at the device. For example, a host may issue a command to a memory module, and a component or feature of the memory module may receive the command and modify the command or the timing of its execution in manner that is invisible or non-disruptive to the host while facilitating operations at the memory module. In some examples, components or features of a memory module may be disabled to effect or introduce latency in operation without affecting timing or operation of a host device. A memory module may operate in different modes that allow for different latencies; the use or introduction of latencies may not affect other features or operability of the memory module.

公开(公告)号：US10700918B2

公开(公告)日：2020-06-30

申请号：US16216742

申请日：2018-12-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Timothy M. Hollis ,  Dean Gans ,  Randon Richards ,  Bruce W. Schober

IPC: H04L25/03 ,  H04L12/24 ,  H04L12/863 ,  G06F13/00 ,  G11C7/10 ,  G11C7/22 ,  G11C5/04

Abstract: According to one embodiment, A data buffer is described. The data buffer comprises a first input/output circuit configured to receive and provide a first signal encoded according to a first communications protocol, a second input/output circuit configured to receive and provide a second signal encoded according to a second communications protocol, and a conversion circuit coupled to the first and second input/output circuits and configured to convert the first signal to the second signal and to convert the second signal to the first signal.