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公开(公告)号：US20210183445A1
公开(公告)日：2021-06-17
申请号：US17162693
申请日：2021-01-29
Applicant: Micron Technology, Inc.
Inventor： Umberto Di Vincenzo , Riccardo Muzzetto , Ferdinando Bedeschi
Abstract: The present disclosure includes apparatuses, methods, and systems for charge separation for memory sensing. An embodiment includes applying a sensing voltage to a memory cell, and determining a data state of the memory cell based, at least in part, on a comparison of an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell before a particular reference time and an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell after the particular reference time.
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公开(公告)号：US20210166756A1
公开(公告)日：2021-06-03
申请号：US17174117
申请日：2021-02-11
Applicant: Micron Technology, Inc.
Inventor： Ferdinando Bedeschi , Riccardo Muzzetto , Umberto Di Vincenzo
Abstract: Methods, systems, devices, and techniques for read operations are described. In some examples, a memory device may include a first transistor (e.g., memory node transistor) configured to receive a precharge voltage at a first gate and output first voltage based on a threshold of the first transistor to a reference node via a first switch. The device may include a second transistor (e.g., a reference node transistor) configured to receive a precharge voltage and output a second voltage based on a threshold of the second transistor to a memory node via a second switch. The first voltage may be modified by a reference voltage and input to the second transistor. The second voltage may be modified by a voltage stored on a memory cell and input to the first transistor. The first and second transistor may output third and fourth voltages to be sampled to a latch.
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公开(公告)号：US10998028B2
公开(公告)日：2021-05-04
申请号：US16544534
申请日：2019-08-19
Applicant: Micron Technology, Inc.
Inventor： Umberto Di Vincenzo , Ferdinando Bedeschi , Riccardo Muzzetto
IPC: G11C11/22
Abstract: Methods and devices for reading a memory cell using a sense amplifier with split capacitors is described. The sense amplifier may include a first capacitor and a second capacitor that may be configured to provide a larger capacitance during certain portions of a read operation and a lower capacitance during other portions of the read operation. In some cases, the first capacitor and the second capacitor are configured to be coupled in parallel between a signal node and a voltage source during a first portion of the read operation to provide a higher capacitance. The first capacitor may be decoupled from the second capacitor during a second portion of the read operation to provide a lower capacitance during the second portion.
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公开(公告)号：US20210098044A1
公开(公告)日：2021-04-01
申请号：US17118035
申请日：2020-12-10
Applicant: Micron Technology, Inc.
Inventor： Ferdinando Bedeschi , Umberto Di Vincenzo
IPC: G11C11/22 , G11C11/404 , G11C11/409 , G11C11/408 , G11C7/10 , G11C11/4091 , G11C7/06 , G11C5/14
Abstract: Methods, systems, and devices for operating a memory cell or cells are described. A capacitor coupled with an access line may be precharged and then boosted such that the charge stored in the capacitor is elevated to a higher voltage with respect to a memory cell. The boosted charge in the capacitor may support sensing operations that would otherwise require a relatively higher voltage. Some embodiments may employ charge amplification between an access line and a sense component, which may amplify signals between the memory cell and the sense component, and reduce charge sharing between these components. Some embodiments may employ “sample-and-hold” operations, which may re-use certain components of a sense component to separately generate a signal and a reference, reducing sensitivity to manufacturing and/or operational tolerances. In some embodiments, sensing may be further improved by employing “self-reference” operations that use a memory cell to generate its own reference.
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公开(公告)号：US10943654B2
公开(公告)日：2021-03-09
申请号：US16905104
申请日：2020-06-18
Applicant: Micron Technology, Inc.
Inventor： Ferdinando Bedeschi , Riccardo Muzzetto , Umberto Di Vincenzo
Abstract: Methods, systems, devices, and techniques for read operations are described. In some examples, a memory device may include a first transistor (e.g., memory node transistor) configured to receive a precharge voltage at a first gate and output first voltage based on a threshold of the first transistor to a reference node via a first switch. The device may include a second transistor (e.g., a reference node transistor) configured to receive a precharge voltage and output a second voltage based on a threshold of the second transistor to a memory node via a second switch. The first voltage may be modified by a reference voltage and input to the second transistor. The second voltage may be modified by a voltage stored on a memory cell and input to the first transistor. The first and second transistor may output third and fourth voltages to be sampled to a latch.
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Patent Agency Ranking
公开(公告)号：US10910054B2
公开(公告)日：2021-02-02
申请号：US16558683
申请日：2019-09-03
Applicant: Micron Technology, Inc.
Inventor： Umberto Di Vincenzo , Riccardo Muzzetto , Ferdinando Bedeschi
Abstract: The present provision includes apparatuses, methods, and systems for charge separation for memory sensing. An embodiment includes applying a sensing voltage to a memory cell, and determining a data state of the memory cell based, at least in part, on a comparison of an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell before a particular reference time and an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell after the particular reference time.
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公开(公告)号：US20200342944A1
公开(公告)日：2020-10-29
申请号：US16927473
申请日：2020-07-13
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , Umberto Di Vincenzo
Abstract: A counter can have a number of sensing components. Each respective sensing component can be configured to sense a respective event and can include a respective first capacitor configured to be selectively coupled to a second capacitor in response to the respective sensing component sensing the respective event. The second capacitor can be configured to be charged to a voltage by each respective first capacitor that is selectively coupled to the second capacitor. The counter can have a comparator with a first input coupled to the second capacitor and a second input coupled to a reference voltage corresponding to a threshold quantity of events. The comparator can be configured to output a signal indicative of the threshold quantity of events being sensed in response to the voltage of the second capacitor being greater than or equal to the reference voltage.
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公开(公告)号：US20200090712A1
公开(公告)日：2020-03-19
申请号：US16584547
申请日：2019-09-26
Applicant: Micron Technology, Inc.
Inventor： Ferdinando Bedeschi , Umberto Di Vincenzo
Abstract: Methods, systems, and devices for variable filter capacitance are described. Within a memory device, voltages may be applied to access lines associated with two voltage sources to increase the capacitance provided by the access lines between the two voltage sources. In some cases, the access lines may be in electronic communication with capacitive cells that include a capacitive element and a selection component, and the voltage sources and access lines may be configured to utilize the capacitive elements and the capacitance between the access lines to generate an increase capacitance between the voltage sources. In some cases, decoders may be used to implement certain configurations that generate different capacitance levels. Similarly, sub-decoders may generate different capacitance levels by selecting portions of a capacitive array.
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公开(公告)号：US20200075076A1
公开(公告)日：2020-03-05
申请号：US16121224
申请日：2018-09-04
Applicant: Micron Technology, Inc.
Inventor： Hyun Yoo Lee , Suryanarayana B. Tatapudi , Huy T. Vo , Ferdinando Bedeschi , Umberto Di Vincenzo , Riccardo Muzzetto
IPC: G11C11/22 , G11C11/4091 , G11C11/4094
Abstract: Methods, systems, and devices for a source follower-based sensing architecture and sensing scheme are described. In one example, a memory device may include a sense circuit that includes two source followers that are coupled to each other and to a sense amplifier. A method of operating the memory device may include transferring a digit line voltage to one of the source followers and transferring a reference voltage to the other source follower. After transferring the digit line voltage and the reference voltage, the source followers may be enabled so that signals representative of the digit line voltage and the reference voltage are transferred from the outputs of the source followers to the sense amplifier for sensing.
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公开(公告)号：US20200013447A1
公开(公告)日：2020-01-09
申请号：US16512982
申请日：2019-07-16
Applicant: Micron Technology, Inc.
Inventor： Umberto Di Vincenzo
Abstract: Methods, systems, and devices for time-based access of memory cells in a memory array are described herein. During a sense portion of a read operation, a selected memory cell may be charged to a predetermined voltage level. A logic state stored on the selected memory cell may be identified based on a duration between the beginning of the charging and when selected memory cell reaches the predetermined voltage level. In some examples, time-varying signals may be used to indicate the logic state based on the duration of the charging. The duration of the charging may be based on a polarization state of the selected memory cell, a dielectric charge state of the selected state, or both a polarization state and a dielectric charge state of the selected memory cell.
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