公开(公告)号：US20140073108A1

公开(公告)日：2014-03-13

申请号：US14080671

申请日：2013-11-14

Applicant: Macronix International Co., Ltd.

Inventor： ChiaHua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

IPC: H01L45/00

CPC classification number: H01L45/1608 ,  H01L45/04 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/1625

Abstract: A bistable resistance random access memory is described for enhancing the data retention in a resistance random access memory member. A dielectric member, e.g. the bottom dielectric member, underlies the resistance random access memory member which improves the SET/RESET window in the retention of information. The deposition of the bottom dielectric member is carried out by a plasma-enhanced chemical vapor deposition or by high-density-plasma chemical vapor deposition. One suitable material for constructing the bottom dielectric member is a silicon oxide. The bistable resistance random access memory includes a bottom dielectric member disposed between a resistance random access member and a bottom electrode or bottom contact plug. Additional layers including a bit line, a top contact plug, and a top electrode disposed over the top surface of the resistance random access memory member. Sides of the top electrode and the resistance random access memory member are substantially aligned with each other.

Abstract translation: 描述了双稳态电阻随机存取存储器，用于增强电阻随机存取存储器件中的数据保持。 电介质构件，例如 底部电介质构件位于电阻随机存取存储器构件的下方，其改善了保留信息中的SET / RESET窗口。 底部电介质构件的沉积通过等离子体增强化学气相沉积或通过高密度 - 等离子体化学气相沉积来进行。 用于构造底部电介质构件的一种合适的材料是氧化硅。 双稳态随机存取存储器包括设置在电阻随机存取构件和底部电极或底部接触插塞之间的底部电介质构件。 附加层包括位线，顶部接触插塞和设置在电阻随机存取存储器构件顶表面上的顶部电极。 顶部电极和电阻随机存取存储器构件的侧面基本上彼此对准。

公开(公告)号：US11751407B2

公开(公告)日：2023-09-05

申请号：US17154615

申请日：2021-01-21

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai ,  Hsiang-Lan Lung

IPC: H01L21/77 ,  H10B63/00 ,  G11C13/00 ,  H10N70/20

CPC classification number: H10B63/82 ,  G11C13/0004 ,  H10B63/84 ,  H10N70/231 ,  G11C2213/71

Abstract: A plurality of memory cells in a cross-point array in which the memory cell stacks in the cross-points include a switch element, a conductive barrier layer, and a confined cell structure in series, and having sides aligned within the cross-point area of the corresponding cross-point, the confined cell structure including surfactant spacers within the cross-point area having outside surfaces on a pair of opposing sides of the stack, and a body of programmable resistance memory material confined between inside surfaces of the surfactant spacers. The memory cells can be operated as multi-level cells in a 3D array.

公开(公告)号：US11502105B2

公开(公告)日：2022-11-15

申请号：US17223050

申请日：2021-04-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai ,  Hsiang-Lan Lung

IPC: H01L29/06 ,  H01L27/1159 ,  H01L21/28 ,  H01L27/11597 ,  H01L29/45 ,  H01L21/764 ,  H01L21/285

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The method includes: forming a silicide layer, forming a vertical Si channel layer, wherein the vertical Si channel layer is on an upper surface of the silicide layer, the vertical Si channel layer has a first silicon phase; performing a first annealing step so as to move the silicide layer upward and change a solid phase of the vertical Si channel layer from the first silicon phase to a second silicon phase at an interface of the silicide layer and the vertical Si channel layer, wherein the second silicon phase has a conductivity higher than a conductivity of the first silicon phase.

公开(公告)号：US20200343252A1

公开(公告)日：2020-10-29

申请号：US16394363

申请日：2019-04-25

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai ,  Hsiang-Lan Lung

IPC: H01L27/1157 ,  H01L27/11582 ,  G11C16/04 ,  G11C5/06

Abstract: A memory device comprises a plurality of stacks of word lines alternating with insulating strips, the stacks being separated by trenches, the word lines extending in a first direction. A plurality of columns of vertical conductive structures is disposed in the trenches between adjacent stacks. Multi-layer films of memory material and channel material are disposed on sidewalls of word lines on at least one side of the trenches between adjacent vertical conductive structures in the plurality of vertical conductive structure, the channel material in ohmic contact with the vertical conductive structures. At locations of vertical conductive structures in the plurality of vertical conductive structures, the sidewalls of the word lines are recessed between insulating strips in the stacks to form recesses on the sidewalls of the word lines to isolate the word lines from vertical conductive structures.

公开(公告)号：US20200227432A1

公开(公告)日：2020-07-16

申请号：US16247079

申请日：2019-01-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai ,  Hsiang-Lan Lung

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L23/522 ,  H01L21/28 ,  H01L21/768

Abstract: A memory device comprises a stack of conductive strips separated by insulating layers on a substrate, and a vertical channel structure disposed in a hole through the stack of conductive strips to the substrate. A vertical channel structure is disposed in a hole through the stack of conductive strips to the substrate. Charge storage structures are disposed at cross points of the conductive strips and the vertical channel structure, the charge storage structures including multiple layers of materials. The insulating layers have sidewalls recessed from the vertical channel structure. A charge storage layer of the multiple layers of materials of the charge storage structures lines sidewalls of the insulating layers. Dielectric material is disposed between the vertical channel structure and the charge storage layer on sidewalls of the insulating layers.

公开(公告)号：US10453856B1

公开(公告)日：2019-10-22

申请号：US15938695

申请日：2018-03-28

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai ,  Hsiang-Lan Lung

IPC: H01L27/11 ,  H01L29/792 ,  H01L29/66 ,  H01L27/1157 ,  H01L27/11582

Abstract: A memory device, which can be configured as a 3D NAND flash memory, includes a stack of conductive strips and an opening through the stack exposing sidewalls of conductive strips on first and second sides of the opening. Some of the conductive strips in the stack are configured as word lines. Data storage structures are disposed on the sidewalls of the stack. A vertical channel film is disposed vertically in contact with the data storage structures. The vertical channel film is connected at a proximal end to an upper channel pad over the stack, and at a distal end to a lower channel pad disposed in a lower level of the opening. The upper and lower channel pads may comprise an epitaxial semiconductor and be thicker than the vertical channel film disposed on the sidewalls of the stack.

公开(公告)号：US10170467B2

公开(公告)日：2019-01-01

申请号：US14919821

申请日：2015-10-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai ,  Kuang-Hao Chiang ,  Dai-Ying Lee

IPC: H01L21/8229 ,  H01L27/108 ,  H01L27/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L21/265 ,  H01L21/266 ,  H01L27/11524 ,  H01L27/11556

Abstract: A 3D semiconductor memory device includes a semiconductor substrate, a source line, a gate line and a plurality of memory cells connected in series. The semiconductor substrate has a protruding portion. The source line is disposed in the semiconductor substrate and partially extending below the protruding portion. The gate line is configured to surround and cover the protruding portion and electrically separated from the source line and the protruding portion. The memory cells are disposed on the semiconductor substrate and connected in series to the protruding portion at a top surface thereof.

公开(公告)号：US10163926B2

公开(公告)日：2018-12-25

申请号：US15595974

申请日：2017-05-16

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai ,  Hsiang-Lan Lung

IPC: H01L21/8228 ,  H01L27/11582 ,  H01L27/1157 ,  H01L29/423 ,  H01L21/28 ,  H01L23/535

Abstract: A memory device memory device includes a multi-layers stack, a charge-trapping layer, a first channel layer and a SSL switch. The multi-layers stack includes a plurality of insulating layers, a plurality of conductive layers alternatively stacked with the insulating layers and at least one first through opening passing through the conductive layers. The charge-trapping layer blankets over a sidewall of the first through opening. The first channel layer is disposed in the first through opening. The SSL switch is disposed on the multi-layers stack and includes a second channel layer, a gate dielectric layer and a gate. The second channel layer is disposed on and electrically contacting to the first channel layer. The gate dielectric layer is disposed on the second channel layer and made of a material other than that for making the charge-trapping layer. The gate is disposed on the gate dielectric layer.

公开(公告)号：US10157963B1

公开(公告)日：2018-12-18

申请号：US15712474

申请日：2017-09-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Dai-Ying Lee ,  Erh-Kun Lai ,  Feng-Min Lee

IPC: H01L27/24 ,  H01L45/00

Abstract: A semiconductor device includes a substrate and a memory structure disposed above the substrate. An embodied memory structure includes a bottom electrode disposed above the substrate, a barrier layer disposed at the bottom electrode, a resistance switching layer disposed on the bottom electrode and above the barrier layer, and a top electrode disposed on the resistance switching layer and covering the resistance switching layer. A bottom surface of the resistance switching layer is spaced apart from an uppermost surface of the barrier layer by a distance.

公开(公告)号：US10141221B1

公开(公告)日：2018-11-27

申请号：US15652325

申请日：2017-07-18

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai ,  Hsiang-Lan Lung

IPC: H01L21/768 ,  H01L21/3213 ,  H01L21/3205 ,  H01L27/11582 ,  H01L21/311

Abstract: A method of manufacturing a three-dimensional (3D) stacked semiconductor structure is provided. A multi-layered stack is formed above a substrate, and the multi-layered stack comprises a plurality of nitride layers and polysilicon layers arranged alternately. Several channel holes are formed vertically to the substrate. The multi-layered stack is patterned to form linear spaces between the channel holes, wherein the linear spaces extend downwardly for being vertical to the substrate and to expose sidewalls of the nitride layers and the polysilicon layers. Then, the polysilicon layers are replaced with insulating layers having air-gaps through the linear spaces, and the nitride layers are replaced with conductive layers through the linear spaces.