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    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    1.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
    半导体器件及其制造方法

    公开(公告)号：US20160247814A1

    公开(公告)日：2016-08-25

    申请号：US14730340

    申请日：2015-06-04

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Erh-Kun Lai ,  Kuang-Hao Chiang

    IPC: H01L27/115 ,  H01L21/311 ,  H01L21/28

    CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L21/31144 ,  H01L21/764 ,  H01L29/4234

    Abstract: A semiconductor device and a manufacturing method of a semiconductor device thereof are provided. The manufacturing method includes the following steps. Two stacked structures are formed a substrate. Each of the stacked structures includes a plurality of gate layers, a plurality of gate insulating layers and a top insulating layer. A charge trapping structure and a channel layer are formed. The charge trapping structure includes a plurality of first dielectric layers and a plurality of second dielectric layers. Part of each of first dielectric layers is etched and part of each of second dielectric layers is etched to expose part of the channel layer. A landing pad layer is formed on the first dielectric layers and the second dielectric layers to connect the channel layer.

    Abstract translation: 提供半导体器件及其半导体器件的制造方法。 该制造方法包括以下步骤。 两个堆叠结构形成基板。 每个堆叠结构包括多个栅极层，多个栅极绝缘层和顶部绝缘层。 形成电荷捕获结构和沟道层。 电荷捕获结构包括多个第一电介质层和多个第二电介质层。 蚀刻每个第一电介质层的一部分，蚀刻每个第二电介质层的一部分以暴露沟道层的一部分。 在第一电介质层和第二电介质层上形成着接垫层以连接沟道层。

    RESISTIVE MEMORY DEVICE WITH RING-SHAPED METAL OXIDE ON TOP SURFACES OF RING-SHAPED METAL LAYER AND BARRIER LAYER
    5.
    发明申请
    RESISTIVE MEMORY DEVICE WITH RING-SHAPED METAL OXIDE ON TOP SURFACES OF RING-SHAPED METAL LAYER AND BARRIER LAYER 有权
    具有环形金属氧化物的环形存储器件在环形金属层和障碍层的顶表面上

    公开(公告)号：US20160225983A1

    公开(公告)日：2016-08-04

    申请号：US14603390

    申请日：2015-01-23

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Yu-Yu Lin ,  Feng-Min Lee ,  Kuang-Hao Chiang ,  Ming-Hsiu Lee

    IPC: H01L45/00

    CPC classification number: H01L45/146 ,  H01L45/04 ,  H01L45/124 ,  H01L45/1633

    Abstract: A resistive memory device is provided, comprising a bottom electrode, a patterned dielectric layer with a via formed on the bottom electrode, a barrier layer formed at sidewalls and a bottom surface of the via as a liner, a ring-shaped metal layer formed at sidewalls and a bottom surface of the barrier layer, and a ring-shaped metal oxide formed on a top surface of the ring-shaped metal layer.

    Abstract translation: 提供了一种电阻式存储器件，包括底部电极，形成在底部电极上的通孔的图案化电介质层，形成在通孔的侧壁和底部表面的阻挡层作为衬垫，形成在环形金属层 侧壁和阻挡层的底表面，以及形成在环形金属层的顶表面上的环形金属氧化物。

    Memory structure and manufacturing method of the same
    9.
    发明授权
    Memory structure and manufacturing method of the same 有权

    公开(公告)号：US09748262B1

    公开(公告)日：2017-08-29

    申请号：US15097335

    申请日：2016-04-13

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Erh-Kun Lai ,  Kuang-Hao Chiang

    IPC: H01L27/115 ,  H01L27/11582 ,  H01L27/11556 ,  H01L29/49

    CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/4916 ,  H01L29/495

    Abstract: A memory structure and a manufacturing method thereof are provided. The memory structure includes a bottom oxide layer, a first conductive layer on the bottom oxide layer, a first insulation recess, a plurality of insulating layers on the first conductive layer, a plurality of second conductive layers, a second insulation recess, a channel layer on a sidewall of the second insulation recess, and a memory layer located between the channel layer and the second conductive layers. The first insulation recess has a first width and penetrates through the first conductive layer. The second conductive layers and the insulating layers are interlacedly stacked, and the second conductive layers are electrically isolated from the first conductive layer. The second insulation recess located on the first insulation recess has a second width larger than the first width and penetrates through the insulating layers and the second conductive layers.

    Semiconductor device and manufacturing method thereof
    10.
    发明授权
    Semiconductor device and manufacturing method thereof 有权
    半导体装置及其制造方法

    公开(公告)号：US09576972B2

    公开(公告)日：2017-02-21

    申请号：US14730340

    申请日：2015-06-04

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Erh-Kun Lai ,  Kuang-Hao Chiang

    IPC: H01L27/115 ,  H01L21/28 ,  H01L21/311 ,  H01L29/423 ,  H01L21/764

    CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L21/31144 ,  H01L21/764 ,  H01L29/4234

    Abstract: A semiconductor device and a manufacturing method of a semiconductor device thereof are provided. The manufacturing method includes the following steps. Two stacked structures are formed a substrate. Each of the stacked structures includes a plurality of gate layers, a plurality of gate insulating layers and a top insulating layer. A charge trapping structure and a channel layer are formed. The charge trapping structure includes a plurality of first dielectric layers and a plurality of second dielectric layers. Part of each of first dielectric layers is etched and part of each of second dielectric layers is etched to expose part of the channel layer. A landing pad layer is formed on the first dielectric layers and the second dielectric layers to connect the channel layer.

    Abstract translation: 提供半导体器件及其半导体器件的制造方法。 该制造方法包括以下步骤。 两个堆叠结构形成基板。 每个堆叠结构包括多个栅极层，多个栅极绝缘层和顶部绝缘层。 形成电荷捕获结构和沟道层。 电荷捕获结构包括多个第一电介质层和多个第二电介质层。 蚀刻每个第一电介质层的一部分，蚀刻每个第二电介质层的一部分以暴露沟道层的一部分。 在第一电介质层和第二电介质层上形成着接垫层以连接沟道层。

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